SO 54 T Search Results

Contextual Info: LG Semicûfi GMM26417228ATG Co., Ltd. 16, 777,216 w o r d s x 6 4 b i t SYNCHRONOUS DYNAMIC RAM SO-DIMM Description The GMM26417228ATG is a 16M x 64 bits Synchronous Dynamic RAM SO-DIMM which is assembled 8 pieces of 16M x 8bits Synchronous DRAMs in 54 pin TSOP II

Contextual Info: GMM26417228ANTG LG S em ico n Co, 16,777,216 WORDS x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM Description The GMM26417228ANTG is a 16M x 64 bits Synchronous Dynamic RAM SO-DIMM which is assembled 8 pieces of 8M x 16bits Synchronous DRAMs in 54 pin TSOP II package and one 2048 bit EEPROM in 8 pin

MUX 74157

Abstract: 74157 mux 74153 mux mux 74153 74298 quad 2 in mux ttl 74157 TTL 74153 MUX 74151 pin diagram of 74153 74153 8bit
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 H I M Ew Dl Ü2 D156 54/74298, 54LS/74LS298 D155 9309, 93L09 12 11 10 D3 9 4 5 6 7 3 1 3 - So 5 - Ra 3 - Si 6 o o o ec UJ 7 N N 14 15

Contextual Info: G M M 26417227A N T G LG S e m ic o n C o , 16,777,216 WORDS x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM Description The GMM26417227ANTG is a 16M x 64 bits Synchronous Dynamic RAM SO-DIMM which is assembled 8 pieces of 8M x 16bits Synchronous DRAMs in 54 pin TSOP II

Contextual Info: LG Semicûfi G M M 26417227A T G Co., Ltd. 16, 777,216 w o r d s x 6 4 b i t SYNCHRONOUS DYNAMIC RAM SO-DIMM Description The GMM26417227ATG is a 16M x 64 bits Synchronous Dynamic RAM SO-DIMM which is assembled 8 pieces of 16M x 8bits Synchronous DRAMs in 54 pin TSOP II

Contextual Info: CUST OMER PR ODU CT SPECIFICATION S H E E T BB02-HA BB02-HA - 2. 54 mm 0, 1" PI N H E A D E R , S I N G L E R O W , T H R O U G H H O L E 02 T O 40 C O N T A C T S FEATURES 2. 54 A ( 6. 00) EASILY BREAKAB LE NOTCHES 2. 54 S T A N D O F F S FACILITATE POST SO LD ER CLEANING.

7472 PIN DIAGRAM

Abstract: 74574 74LS112 74LS74 7473 dual JK 7472 ttl TTL 7472 7472 ci CI 7473 pin diagram of ttl 7476
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE ui 3 Q </> “ UI 0 (9 D50 9000 D51 9001 D54 54/7470 13 2 A zz J So 0 g1 o° CP = Q. 1 H H (0 2 O O Q. EDGE-TRIGGERED ¡so J. So O « J. S d 0 —6 CP J . KC Äo Qo -n — J— K Q CD Vcc = Pin 14

SD512M16VS1605

Contextual Info: MEMORY MODULE SDRam 32Mx16-SOP Synchronous Dynamic Ram MODULE 3D SD512M16VS1605 512Mbit SDRam organized as 32Mx16, based on 32Mx16 Pin Assignment Top View SO P 54 - (Pitch : 0.80 m m ) Features - Organized as 32Mx16-bit. - Single +3.3V power supply. - Fully synchronous ; all signals registered on positive edge of

AD8551

Abstract: AD8551AR AD8552 AD8554 AD8534
Contextual Info: a Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifier Preliminary AD8551/52/54 8-Lead Epoxy DIP N Suffix 8-Lead SO (R Suffix) FEATURES Low Offset Voltage: 5 µV Input Offset Drift: 0.03 µV/°C Rail-to-Rail Input and Output Swing 5 V Single-Supply Operation

westinghouse power rectifiers

Abstract: WESTINGHOUSE RECTIFIERS 2N2753 WESTINGHOUSE rectifier Westinghouse Semiconductor Westinghouse Power rectifier Westinghouse 54-161 41A hall 2N2740 2N2739
Contextual Info: POWEREX INC JEDEC ty p es 2N27392N2754 silicon pow er tra n sisto rs > • technical dala for switching, regulator and amplifier applications -J co *0 54-661 20 amperes • 200 watts collector-to-emitter voltage SO to 200 volts O' r \j i» 8 page 9 application

si7489dp

Abstract: Si7489DP-T1-E3
Contextual Info: New Product Si7489DP Vishay Siliconix P-Channel 100-V D-S MOSFET FEATURES PRODUCT SUMMARY rDS(on) (Ω) ID (A)a 0.041 at VGS = - 10 V - 28 0.047 at VGS = - 4.5 V - 28 VDS (V) - 100 Qg (Typ) • TrenchFET Power MOSFET RoHS 54 nC COMPLIANT PowerPAK SO-8 S

74198 shift register

Abstract: 74198 74198PC 54198DM 54198FM 74198DC 74198FC
Contextual Info: 198 CONNECTION DIAGRAM PINOUT A '54/74198 £YC;>7</<? 8-BIT R/L SHIFT REGISTER DESCRIPTION — The '198 features synchronous parallel load, hold, shift right and shift left modes, as determ ined by the Select So, Si inputs. State changes are initiated by the rising edge of the clock. An asynchronous Master

Si7858ADP

Abstract: Si7858ADP-T1-E3 Si7858ADP-T1-GE3 S-80440-Rev
Contextual Info: Si7858ADP Vishay Siliconix N-Channel 12-V D-S MOSFET FEATURES PRODUCT SUMMARY VDS (V) 12 RDS(on) (Ω) ID (A) 0.0026 at VGS = 4.5 V 29 0.0037 at VGS = 2.5 V 23 Qg (Typ.) 54 PowerPAK SO-8 • New Low Thermal Resistance PowerPAK Package with Low 1.07 mm Profile

Si7858ADP

Abstract: Si7858ADP-T1-E3 Si7858ADP-T1-GE3
Contextual Info: Si7858ADP Vishay Siliconix N-Channel 12-V D-S MOSFET FEATURES PRODUCT SUMMARY VDS (V) 12 RDS(on) (Ω) ID (A) 0.0026 at VGS = 4.5 V 29 0.0037 at VGS = 2.5 V 23 Qg (Typ.) 54 PowerPAK SO-8 • New Low Thermal Resistance PowerPAK Package with Low 1.07 mm Profile

Si7380ADP-T1-E3

Abstract: 80439 SI7380ADP
Contextual Info: Si7380ADP Vishay Siliconix N-Channel 30-V D-S MOSFET FEATURES PRODUCT SUMMARY RDS(on) (Ω) ID (A)a 0.003 at VGS = 10 V 40 0.0035 at VGS = 4.5 V 40 VDS (V) 30 Qg (Typ.) 54 nC PowerPAK SO-8 • • • • Halogen-free available TrenchFET Power MOSFET PWM Optimized

Contextual Info: Si4143DY www.vishay.com Vishay Siliconix P-Channel 30 V D-S MOSFET FEATURES PRODUCT SUMMARY RDS(on) (Ω) MAX. ID (A) d 0.0062 at VGS = -10 V -25.3 VDS (V) -30 0.0074 at VGS = -6 V -23.2 0.0092 at VGS = -4.5 V -20.8 Qg (TYP.) 54 nC SO-8 Single D 8 D 7 D 6

74198 shift register

Abstract: 54198DM 54198FM 74198DC 74198FC 74198PC
Contextual Info: f ft/ i/s - csj CONNECTION DIAGRAM PINOUT A 54/74198 8-BIT R/L SHIFT REGISTER DESCRIPTION— The '198 features synchronous parallel load, hold, shift right and shift left modes, as determined by the Select So, Si inputs. State changes are initiated by the rising edge of the clock. An asynchronous Master

aa2c

Contextual Info: S i RECTANGULAR SOLID STATE LAMPS OPTOELECTRONICS HIGH EFFICIENCY RED YELLOW HIGH EFFICIENCY GREEN PACKAGE DIMENSIONS i HLMP-0300/1 HLMP-0400/1 HLMP-0503/4 DESCRIPTION SO 018 0 45 NOM INAL _ 2 PLACES 100 |2_5d) 090 (2 29) 315 (800) 100(2 54) NOMINAL 290 |7.37)

Contextual Info: SiR664DP Vishay Siliconix N-Channel 60 V D-S MOSFET FEATURES PRODUCT SUMMARY VDS (V) RDS(on) () Max. ID (A) 0.0060 at VGS = 10 V 60a 0.0075 at VGS = 6 V 60a 0.0095 at VGS = 4.5 V 54 60 Qg (Typ.) 12 nC APPLICATIONS PowerPAK SO-8 S 6.15 mm • Primary Side Switching

ic 74198

Abstract: 74198 shift register
Contextual Info: 198 CONNECTION DIAGRAM PINOUT A 54/74198 8-BIT R/L SHIFT REGISTER D E SC R IPTIO N — The '198 features synchronous parallel load, hold, shift right and shift left modes, as determ ined by the Select So, Si inputs. State changes are initiated by the rising edge of the clock. An asynchronous Master

RA12

Contextual Info: 16Mx64 bits PC100 SDRAM SO DIMM based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh HYM72V16M656T6 Series DESCRIPTION The HYM72V16M656T6 -Series are high speed 3.3-Volt Synchronous DRAM Modules composed of four 16Mx16 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM on a 144-pin Zig Zag Dual pin glass-epoxy

Contextual Info: 16Mx64 bits PC100 SDRAM SO DIMM based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh HYM72V16M656B L T6 Series DESCRIPTION The HYM72V16M656B(L)T6 -Series are high speed 3.3-Volt Synchronous DRAM Modules composed of four 16Mx16 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM on a 144-pin Zig Zag Dual pin glass-epoxy

74LS152

Abstract: TTL 74153 74157 54LS ttl 74157 74170 74LS151 74S153 74S253 93L09
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D154 54/74170, 54LS/74LS170, 54LS/74LS670 HIM 15 Ew Wa 1 3 - Wb 5 - Ra 4 - Rb 2 Ü2 Dl 3 12 11 10 D3 1 3 - So 3 - Si o 6 o o ec UJ TTTTf 10 4 5 9 7 6 Ì2a l3a lob lib 3 3 14 15 5 6

RA12

Contextual Info: 16Mx64 bits PC100 SDRAM SO DIMM based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh HYM72V16M656B L T6 Series DESCRIPTION The HYM72V16M656B(L)T6 -Series are high speed 3.3-Volt Synchronous DRAM Modules composed of four 16Mx16 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM on a 144-pin Zig Zag Dual pin glass-epoxy