SO 54 T Search Results

Contextual Info: GMM26417228ANTG LG S em ico n Co, 16,777,216 WORDS x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM Description The GMM26417228ANTG is a 16M x 64 bits Synchronous Dynamic RAM SO-DIMM which is assembled 8 pieces of 8M x 16bits Synchronous DRAMs in 54 pin TSOP II package and one 2048 bit EEPROM in 8 pin

MUX 74157

Abstract: 74157 mux 74153 mux mux 74153 74298 quad 2 in mux ttl 74157 TTL 74153 MUX 74151 pin diagram of 74153 74153 8bit
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 H I M Ew Dl Ü2 D156 54/74298, 54LS/74LS298 D155 9309, 93L09 12 11 10 D3 9 4 5 6 7 3 1 3 - So 5 - Ra 3 - Si 6 o o o ec UJ 7 N N 14 15

Contextual Info: G M M 26417227A N T G LG S e m ic o n C o , 16,777,216 WORDS x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM Description The GMM26417227ANTG is a 16M x 64 bits Synchronous Dynamic RAM SO-DIMM which is assembled 8 pieces of 8M x 16bits Synchronous DRAMs in 54 pin TSOP II

Contextual Info: CUST OMER PR ODU CT SPECIFICATION S H E E T BB02-HA BB02-HA - 2. 54 mm 0, 1" PI N H E A D E R , S I N G L E R O W , T H R O U G H H O L E 02 T O 40 C O N T A C T S FEATURES 2. 54 A ( 6. 00) EASILY BREAKAB LE NOTCHES 2. 54 S T A N D O F F S FACILITATE POST SO LD ER CLEANING.

SD512M16VS1605

Contextual Info: MEMORY MODULE SDRam 32Mx16-SOP Synchronous Dynamic Ram MODULE 3D SD512M16VS1605 512Mbit SDRam organized as 32Mx16, based on 32Mx16 Pin Assignment Top View SO P 54 - (Pitch : 0.80 m m ) Features - Organized as 32Mx16-bit. - Single +3.3V power supply. - Fully synchronous ; all signals registered on positive edge of

AD8551

Abstract: AD8551AR AD8552 AD8554 AD8534
Contextual Info: a Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifier Preliminary AD8551/52/54 8-Lead Epoxy DIP N Suffix 8-Lead SO (R Suffix) FEATURES Low Offset Voltage: 5 µV Input Offset Drift: 0.03 µV/°C Rail-to-Rail Input and Output Swing 5 V Single-Supply Operation

74198 shift register

Abstract: 74198 74198PC 54198DM 54198FM 74198DC 74198FC
Contextual Info: 198 CONNECTION DIAGRAM PINOUT A '54/74198 £YC;>7</<? 8-BIT R/L SHIFT REGISTER DESCRIPTION — The '198 features synchronous parallel load, hold, shift right and shift left modes, as determ ined by the Select So, Si inputs. State changes are initiated by the rising edge of the clock. An asynchronous Master

Si7858ADP

Abstract: Si7858ADP-T1-E3 Si7858ADP-T1-GE3 S-80440-Rev
Contextual Info: Si7858ADP Vishay Siliconix N-Channel 12-V D-S MOSFET FEATURES PRODUCT SUMMARY VDS (V) 12 RDS(on) (Ω) ID (A) 0.0026 at VGS = 4.5 V 29 0.0037 at VGS = 2.5 V 23 Qg (Typ.) 54 PowerPAK SO-8 • New Low Thermal Resistance PowerPAK Package with Low 1.07 mm Profile

Si7858ADP

Abstract: Si7858ADP-T1-E3 Si7858ADP-T1-GE3
Contextual Info: Si7858ADP Vishay Siliconix N-Channel 12-V D-S MOSFET FEATURES PRODUCT SUMMARY VDS (V) 12 RDS(on) (Ω) ID (A) 0.0026 at VGS = 4.5 V 29 0.0037 at VGS = 2.5 V 23 Qg (Typ.) 54 PowerPAK SO-8 • New Low Thermal Resistance PowerPAK Package with Low 1.07 mm Profile

Si7380ADP-T1-E3

Abstract: 80439 SI7380ADP
Contextual Info: Si7380ADP Vishay Siliconix N-Channel 30-V D-S MOSFET FEATURES PRODUCT SUMMARY RDS(on) (Ω) ID (A)a 0.003 at VGS = 10 V 40 0.0035 at VGS = 4.5 V 40 VDS (V) 30 Qg (Typ.) 54 nC PowerPAK SO-8 • • • • Halogen-free available TrenchFET Power MOSFET PWM Optimized

Contextual Info: Si4143DY www.vishay.com Vishay Siliconix P-Channel 30 V D-S MOSFET FEATURES PRODUCT SUMMARY RDS(on) (Ω) MAX. ID (A) d 0.0062 at VGS = -10 V -25.3 VDS (V) -30 0.0074 at VGS = -6 V -23.2 0.0092 at VGS = -4.5 V -20.8 Qg (TYP.) 54 nC SO-8 Single D 8 D 7 D 6

aa2c

Contextual Info: S i RECTANGULAR SOLID STATE LAMPS OPTOELECTRONICS HIGH EFFICIENCY RED YELLOW HIGH EFFICIENCY GREEN PACKAGE DIMENSIONS i HLMP-0300/1 HLMP-0400/1 HLMP-0503/4 DESCRIPTION SO 018 0 45 NOM INAL _ 2 PLACES 100 |2_5d) 090 (2 29) 315 (800) 100(2 54) NOMINAL 290 |7.37)

Contextual Info: SiR664DP Vishay Siliconix N-Channel 60 V D-S MOSFET FEATURES PRODUCT SUMMARY VDS (V) RDS(on) () Max. ID (A) 0.0060 at VGS = 10 V 60a 0.0075 at VGS = 6 V 60a 0.0095 at VGS = 4.5 V 54 60 Qg (Typ.) 12 nC APPLICATIONS PowerPAK SO-8 S 6.15 mm • Primary Side Switching

ic 74198

Abstract: 74198 shift register
Contextual Info: 198 CONNECTION DIAGRAM PINOUT A 54/74198 8-BIT R/L SHIFT REGISTER D E SC R IPTIO N — The '198 features synchronous parallel load, hold, shift right and shift left modes, as determ ined by the Select So, Si inputs. State changes are initiated by the rising edge of the clock. An asynchronous Master

74LS152

Abstract: TTL 74153 74157 54LS ttl 74157 74170 74LS151 74S153 74S253 93L09
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D154 54/74170, 54LS/74LS170, 54LS/74LS670 HIM 15 Ew Wa 1 3 - Wb 5 - Ra 4 - Rb 2 Ü2 Dl 3 12 11 10 D3 1 3 - So 3 - Si o 6 o o ec UJ TTTTf 10 4 5 9 7 6 Ì2a l3a lob lib 3 3 14 15 5 6

RA12

Contextual Info: 16Mx64 bits PC100 SDRAM SO DIMM based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh HYM72V16M656B L T6 Series DESCRIPTION The HYM72V16M656B(L)T6 -Series are high speed 3.3-Volt Synchronous DRAM Modules composed of four 16Mx16 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM on a 144-pin Zig Zag Dual pin glass-epoxy

74157 pin diagram

Abstract: TTL 74153 74s157 pin diagram fairchild 9312 74157 D157 Fairchild 9322 93L09 74S153 93L22
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL - T T L D154 54/74170, 54LS/74LS170, 54LS/74LS670 15 H 1 2 3 12 11 10 I M Ew Ü2 Dl D3 loa I la 1 3 - W b 1 3 - So 5 - Ra 3 - S i N T 14 11 10 6 T 7 E lo 11 3 3 5 6 S 11— 0 CP 7 lOb 11b lOc l i e

MAX2332

Abstract: 74LS152FC 74LS152 74152A
Contextual Info: 152 CO NNECTIO N DIAGRAM PINOUT A J j/54/74152A 154LS/74LSH52 i4 [ 7 Ï 3 Vcc 13U 13] Is 8 -IN P U T M U LTIPLEXER [T m «e ii [ 7 11] l5 io [ £ ÏÔ1 So Z [6 T | Si 12 g n d [T D ESC R IPTIO N — The ’ 152 is a high speed 8-inp ul digital m ultiplexer. It

74LS152

Abstract: 74151A multiplexers 74151 PIN DIAGRAM 74151A 74ls151 pin diagram 74LS151 pin diagram of 74157 74152A pin diagram of 74153 TTL 74153
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL - T T L D154 54/74170, 54LS/74LS170, 54LS/74LS670 H 1 2 3 12 11 10 I M Ew Dl Ü2 D3 loa I la 1 3 - W b 1 3 - So 5 - Ra 3 - S i 4 - Rb 6 7 14 2 E lo 11 3 3 4 5 6 5 7 6 S 11— 0 CP lOb 11b lOc l i e

CI 7446

Abstract: CI 74141 cI 74ls47 CI 7447 CI 7448 ci 7445 7-seg ANODE COMMON CI 74LS48 TTL 7446 BCD D147
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 i Ao A RBO a A 2 b A3 e d 1 El e 13 12 11 10 RBI f 9 E 9 15 3 2 4 m l 14 6 m Do MR TTTTTTTT 4 D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

LF298

Abstract: K010 LF198 LF398 LF398A din-210 SHC29B
Contextual Info: • • • • ca r< ‘¡r V Sj Q 1 V H öS X• co ^ S V iM , 8t-: £ *3 ¡5 •5+- mi?i miili © püjl IOTI -54- -M- • H SO O m S i— II :Sj H ÍD S? 3 t s £ "vr■ ü> S fiV'* ^ i?' ^ > > > id -i r i f Tritìi nuil miji p ? p E P BPiS g ffflffl.

CA001

Abstract: D0232 3824B iss214
Contextual Info: HC2 TIilO 23 E d • 5 ^ 1 2 7 7 oDooooi 7 « n e e 7 ^ - / 3 -o r iTie CA001 GPS C/A CODE CODE GENERATOR (Preliminary) CCt+l> 9 CCtJ 10 CCt-lJ ii GND 12 24 23 22 21 20 19 18 17 16 IS 14 13 Vcc CLK 59* 58* S7* 56* 55* 54* S3« 52* 51» SO* %% w CA001 C/'A Cod«

7475 D flip-flop

Abstract: quad D flip-flop 74175 pin 4 bit shift register 7494 pin diagram latch 74ls574 7477 D latch 74174 shift register 9374 74LS173 4 bit 3 state quad register 74LS279 D flip-flop 74175 pin
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 i Ao A R BO a A 2 b A 3 e d 1 E l RBI e 13 12 11 10 E 9 f 9 15 3 2 4 m l 14 6 m Do M R TTTTTTTT 4 D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

TTL 74ls74

Abstract: 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL M A S T E R /S LA V E E D G E -T R IG G E R E D D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi J Q (3 CP o K Z 2 — J SD 0 _6 Co (3 “LT in > z o Q J CP I- 3 a. 3 O So J - Ö K 4-0