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    smj320c30-50 Datasheets

    smj320c30-50 datasheet (1)

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    SMJ320C30-50 Texas Instruments DIGITAL SIGNAL PROCESSOR Original PDF

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    1991 - TAG 8442

    Abstract: tag 8634 tag 8418 SPRU031D tag 8610 3055 smd smj320c31hfgm33 SMJ320C30 SMJ320C30-40 SMJ320C31
    Text: ) 33 MFLOPS 16.7 MIPS ­ SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS One 4K-Word × 32 , Performance ­ SMJ320C31-33 (60-ns Cycle) 33.3 MFLOPS 16.7 MIPS ­ SMJ320C31-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS ­ SMJ320C31- 50 (40-ns Cycle) 50 MFLOPS 25 MIPS Flexible Boot-Program Loader One Serial Port , Package (GFA Suffix) ­ 244-Pad JEDEC-Standard TAB Frame SMD Approval for 33-, 40-, and 50 -MHz Versions , ÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 1 50 2 99 POST OFFICE BOX 1443 ·


    Original     		PDF SMJ320C30, SMJ320C31 SGUS014B MIL-PRF-38535 32-Bit 64-Word 24-Bit TAG 8442 tag 8634 tag 8418 SPRU031D tag 8610 3055 smd smj320c31hfgm33 SMJ320C30 SMJ320C30-40 SMJ320C31

    1991 - Not Available

    Abstract: No abstract text available
    Text: -38535 (QML) Performance - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS , processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40 , 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary Registers and Two Auxiliary , flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in , DVDD DVSS VDD VSS 148 147 VDD VSS DVSS DVDD 49 50 98 99 The SMJ320C30 can perform parallel


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    K1363

    Abstract: SMJ320C30 SMJ320C30-40 SMJ320C30-50 FGM40 dxo crystal oscillator
    Text: -40 ( 50 -ns Cycle) 40 Million Floating-Point Operations Per Second (MFLOPS) 20 Million Instructions Per Second (MIPS) - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word x 32-Bit Single-Cycle , -ns single-cycle execution time, 5% supply • SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply A , , Floating-Point, and Logical Operations SMD Approval for 40- and 50 -MHz Versions Two Address Generators With , digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS


    OCR Scan     		PDF SMJ320C30 SGUS014D- MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word K1363 SMJ320C30 SMJ320C30-40 SMJ320C30-50 FGM40 dxo crystal oscillator

    1991 - SMJ320C30

    Abstract: SMJ320C30-40 SMJ320C30-50
    Text: MIL-PRF-38535 (QML) Performance - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks Validated , -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two , signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS. The


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word SMJ320C30 SMJ320C30-40 SMJ320C30-50

    1991 - Not Available

    Abstract: No abstract text available
    Text: SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32 , that can be designed into systems currently using costly bit-slice processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary , digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    1991 - Not Available

    Abstract: No abstract text available
    Text: -38535 (QML) Performance - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS , processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40 , 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary Registers and Two Auxiliary , flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in , DVDD DVSS VDD VSS 148 147 VDD VSS DVSS DVDD 49 50 98 99 The SMJ320C30 can perform parallel


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    1991 - 80586 microprocessor pin diagram

    Abstract: 80586 181-pin bit-slice
    Text: MIL-PRF-38535 (QML) Performance ­ SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS ­ SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks Validated Ada , SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply SMJ320C30-50 : 40-ns single-cycle execution time , 196-Pin Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 , execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in hardware that


    Original     		PDF SMJ320C30 SGUS014F MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word 80586 microprocessor pin diagram 80586 181-pin bit-slice

    5962-9052603mua

    Abstract: No abstract text available
    Text: ) 16.7 Million instructions Per Second (MIPS) - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word x 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks , , 5% supply SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply A Please be aware that an , -Pin Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) SMD Approval for 33-, 40-, and 50 , execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in hardware that


    OCR Scan     		PDF SMJ320C30 SGUS014C- MIL-PRF-38535 SMJ320C30-33 60-ns SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 5962-9052603mua

    1991 - SMJ320C31

    Abstract: SMJ320C30 SMJ320C30-40 238 pin PGA socket 41500
    Text: ) 33 MFLOPS 16.7 MIPS ­ SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS One 4K-Word × 32 , Performance ­ SMJ320C31-33 (60-ns Cycle) 33.3 MFLOPS 16.7 MIPS ­ SMJ320C31-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS ­ SMJ320C31- 50 (40-ns Cycle) 50 MFLOPS 25 MIPS Flexible Boot-Program Loader One Serial Port , Package (GFA Suffix) ­ 244-Pad JEDEC-Standard TAB Frame SMD Approval for 33-, 40-, and 50 -MHz Versions , ÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 1 50 2 99 POST OFFICE BOX 1443 ·


    Original     		PDF SMJ320C30, SMJ320C31 SGUS014B MIL-PRF-38535 32-Bit 64-Word 24-Bit SMJ320C31 SMJ320C30 SMJ320C30-40 238 pin PGA socket 41500

    1991 - SMJ320C30

    Abstract: SMJ320C30-40 SMJ320C30-50 H1376
    Text: MIL-PRF-38535 (QML) Performance - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks Validated , -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two , signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS. The


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word SMJ320C30 SMJ320C30-40 SMJ320C30-50 H1376

    1991 - Not Available

    Abstract: No abstract text available
    Text: SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32 , that can be designed into systems currently using costly bit-slice processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary , digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    1991 - 181pin

    Abstract: No abstract text available
    Text: -38535 (QML) Performance - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS , processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40 , 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary Registers and Two Auxiliary , flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in , DVDD DVSS VDD VSS 148 147 VDD VSS DVSS DVDD 49 50 98 99 The SMJ320C30 can perform parallel


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word 181pin

    1991 - 25MIPS

    Abstract: XD31-XD0 qtc h11
    Text: -38535 (QML) Performance - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS , processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40 , 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary Registers and Two Auxiliary , flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in , DVDD DVSS VDD VSS 148 147 VDD VSS DVSS DVDD 49 50 98 99 The SMJ320C30 can perform parallel


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word 25MIPS XD31-XD0 qtc h11

    1991 - 238 pin PGA socket

    Abstract: SMJ320C31-33 5962-9205802 SMJ320C30 SMJ320C30-40 SMJ320C31 D1392 SMJ320C31GFAM33 SMJ320C3x SPRU031D
    Text: ) 33 MFLOPS 16.7 MIPS ­ SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS One 4K-Word × 32 , Performance ­ SMJ320C31-33 (60-ns Cycle) 33.3 MFLOPS 16.7 MIPS ­ SMJ320C31-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS ­ SMJ320C31- 50 (40-ns Cycle) 50 MFLOPS 25 MIPS Flexible Boot-Program Loader One Serial Port , Package (GFA Suffix) ­ 244-Pad JEDEC-Standard TAB Frame SMD Approval for 33-, 40-, and 50 -MHz Versions , ÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 1 50 2 99 POST OFFICE BOX 1443 ·


    Original     		PDF SMJ320C30, SMJ320C31 SGUS014B MIL-PRF-38535 32-Bit 64-Word 24-Bit 238 pin PGA socket SMJ320C31-33 5962-9205802 SMJ320C30 SMJ320C30-40 SMJ320C31 D1392 SMJ320C31GFAM33 SMJ320C3x SPRU031D

    1991 - Not Available

    Abstract: No abstract text available
    Text: SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32 , that can be designed into systems currently using costly bit-slice processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary , digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    1991 - SMJ320C30

    Abstract: SMJ320C30-40 SMJ320C30-50 b5758
    Text: MIL-PRF-38535 (QML) Performance ­ SMJ320C30-40 ( 50 -ns Cycle) 40 Million Floating-Point Operations Per Second (MFLOPS) 20 Million Instructions Per Second (MIPS) ­ SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 , SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply SMJ320C30-50 : 40-ns single-cycle execution time , , and Logical Operations SMD Approval for 40- and 50 -MHz Versions Two Address Generators With Eight , execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in hardware that


    Original     		PDF SMJ320C30 SGUS014D MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word SMJ320C30 SMJ320C30-40 SMJ320C30-50 b5758

    1991 - Not Available

    Abstract: No abstract text available
    Text: SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32 , that can be designed into systems currently using costly bit-slice processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary , digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    1991 - Not Available

    Abstract: No abstract text available
    Text: SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32 , that can be designed into systems currently using costly bit-slice processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary , digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    1991 - P181 GB

    Abstract: SMJ320C30 SMJ320C30-40 SMJ320C30-50
    Text: MIL-PRF-38535 (QML) Performance - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks Validated , -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two , signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS. The


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word P181 GB SMJ320C30 SMJ320C30-40 SMJ320C30-50

    1991 - Not Available

    Abstract: No abstract text available
    Text: SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32 , that can be designed into systems currently using costly bit-slice processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary , digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    1991 - Not Available

    Abstract: No abstract text available
    Text: SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32 , that can be designed into systems currently using costly bit-slice processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary , digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    1991 - SMJ320C30

    Abstract: SMJ320C30-40 SMJ320C30-50
    Text: to MIL-PRF-38535 (QML) Performance ­ SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS ­ SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks , -40: 50 -ns single-cycle execution time, 5% supply SMJ320C30-50 : 40-ns single-cycle execution time, 5 , Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two , signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS. The


    Original     		PDF SMJ320C30 SGUS014G MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word SMJ320C30 SMJ320C30-40 SMJ320C30-50

    1991 - Not Available

    Abstract: No abstract text available
    Text: Processed to MIL-PRF-38535 (QML) Performance − SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS − SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM , SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution , ˆ’ 196-Pin Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 , up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in hardware that


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word

    2004 - Not Available

    Abstract: No abstract text available
    Text: D Range, QML Processing Processed to MIL-PRF-38535 (QML) Performance - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS 25 MIPS Two 1K-Word × 32 , -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40-ns single-cycle execution time, 5% supply Please , With Nonconductive Tie-Bar (HFG Suffix) SMD Approval for 40- and 50 -MHz Versions Two Address , signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS. The


    Original     		PDF SMJ320C30 SGUS014H 32-Bit MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 64-Word

    1991 - Not Available

    Abstract: No abstract text available
    Text: -38535 (QML) Performance - SMJ320C30-40 ( 50 -ns Cycle) 40 MFLOPS 20 MIPS - SMJ320C30-50 (40-ns Cycle) 50 MFLOPS , processors. D SMJ320C30-40: 50 -ns single-cycle execution time, 5% supply D SMJ320C30-50 : 40 , 40- and 50 -MHz Versions Two Address Generators With Eight Auxiliary Registers and Two Auxiliary , flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in , DVDD DVSS VDD VSS 148 147 VDD VSS DVSS DVDD 49 50 98 99 The SMJ320C30 can perform parallel


    Original     		PDF SMJ320C30 SGUS014H MIL-PRF-38535 SMJ320C30-40 50-ns SMJ320C30-50 40-ns 32-Bit 64-Word
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