SFP LVDS Search Results

Contextual Info: Terasic THDB-SUM SFP HSMC Terasic SFP HSMC Board User Manual Document Version 1.00 AUG 12, 2009 by Terasic Introduction Page Index INTRODUCTION . 1

74729 latch

Abstract: dms 59 to vga SFF8470 pinout DMS59 to vga PS-91525-001 DMS-59 to 15pin QSFP passive connector xaui mini HDMI plug 74752-2301 Micro-D connectors
Contextual Info: I/O Products High Speed Pluggable I/O Solutions Small Form-Factor Pluggable SFP to N-3 Cable to N-8

BCM8155

Abstract: xFP STM-64 GR-253
Contextual Info: BCM8155 Multirate Low-Power 10G RZ/NRZ/Duo-binary Transceiver with 10G Clock FEATURES • Fully integrated multirate CDR, DEMUX, MUX, CMU • 300-pin Multisource Agreement MSA compatible • Compliant with ITU GR-253, XFP, and SFP+ specifications • 16-bit LVDS interface compliant with Optical

BCM8157

Abstract: BCM8154 196-PIN SFP LVDS BCM8156 GR-253
Contextual Info: BCM8157 MULTIRATE LOW-POWER 10G XFI TO SFI-4.1 TRANSCEIVER 8.5 GBPS–11.35 GBPS FEATURES • Fully integrated multirate CDR, DEMUX, MUX, CMU • SONET-compliant serial interface • 300-pin Multisource Agreement (MSA)-compatible • Compliant to ITU GR-253, XFP, and SFP+ specifications

Contextual Info: 19-2268; Rev 0; 3/02 Dual 1.25Gbps Transceiver ♦ CML Interface Exceeds all PECL AC Specifications for 1000Base-SX/LX, GBIC, or SFP Serial Data ♦ Tx Data Retiming with <0.1UI Total Output Jitter Beats IEEE802.3z Requirements ♦ Rx Data and Clock Recovery with 0.75UI Jitter

Contextual Info: M02061 3.3 or 5 Volt Laser Driver IC for Applications to 4.25 Gbps The M02061 is a highly integrated, programmable laser driver intended for SFP/SFF module with data rates up to 4.25 Gbps. Using differential PECL data inputs, the M02061 supplies the bias and modulation current required to

MAX3657

Abstract: MAX3969 MAX3969ETP
Contextual Info: 19-3251; Rev 0; 4/04 200Mbps SFP Limiting Amplifier Features The MAX3969 limiting amplifier with PECL data outputs is ideal for low-cost ATM, Fast Ethernet, FDDI and ESCON fiber optic receivers. The MAX3969 features 1mVP-P input sensitivity and an integrated power detector that senses the input signal

logic diagram of 7432

Contextual Info: 19-3251; Rev 1; 6/06 200Mbps SFP Limiting Amplifier Features The MAX3969 limiting amplifier with PECL data outputs is ideal for low-cost ATM, Fast Ethernet, FDDI and ESCON fiber optic receivers. The MAX3969 features 1mVP-P input sensitivity and an integrated power detector that senses the input signal

M02061G12

Contextual Info: Revision Information This document contains information that is subject to change without notice. Contact Technical Publications for latest revision information. M02061 3.3 or 5 Volt Laser Driver IC for Applications to 4.25 Gbps The M02061 is a highly integrated, programmable laser driver intended for SFP/SFF module with data rates up to

Contextual Info: Dual 2:1 and 1:2 Differential-to-LVDS Multiplexer ICS854S54I DATA SHEET General Description Features The ICS854S54I is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to one of two outputs. This device is

ICS854S54I

Abstract: ICS854S54AKI IFR2042 MO-220
Contextual Info: Dual 2:1 and 1:2 Differential-to-LVDS Multiplexer ICS854S54I DATA SHEET General Description Features The ICS854S54I is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplexer allows one of 2 inputs to be selected HiPerClockS onto one output pin and the 1:2 MUX switches one

Contextual Info: 2013.10.17 AN-518 SGMII Interface Implementation Using Soft CDR Mode of Altera FPGAs Subscribe Send Feedback The Serial Gigabit Media Independent Interface SGMII protocol provides connectivity between the physical layer (PHY) and the Ethernet media controller (MAC). The SGMII solution for Altera FPGAs allows you

QT2225

Abstract: qt2025 s4886 S10124 G.975.1 QT2225-1 S4882 S4884 QT2025-1 S19262
Contextual Info: Transport Products Product Selector Guide Table of Contents Physical Layer Devices Framer/Mappers Datacom PHY S19225

Xenon 175

Abstract: SFP LVDS altera PC680 PM5392 STM-64 SFP PM3388 PM3392 PM5390 hmzd connector SFP altera
Contextual Info: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices May 2003, ver. 1.0 Introduction Application Note 228 The system packet interface level 4–phase 2 SPI-4.2 specification, defined by the Optical Internetworking Forum (OIF), is fast becoming the most

marvel phy 88e1111 reference design

Abstract: 88E1111 schematic diagram of laptop motherboard Marvell PHY 88E1111 Datasheet 88E1111 PHY registers map 88E1111 pinout 2N3904 equivalent Marvell 88E1111 layout guide Marvell 88E1111 vhdl Marvell PHY 88E1111 layout
Contextual Info: Stratix II GX PCI Express Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com Document Version: Document Date: 1.0.1 April 2007 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

AMCC s1212

Abstract: Amcc S1221 amcc CDR SCP6802-GL S1212 S122 S1220 S1221 S4805 S4806
Contextual Info: PRODUC T BRIEF S122 S1220 SONET/SDH/ATM Quad OC-3/12 with Clock Data Recovery CDR Features Description • Complies with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation • On-chip high-frequency PLLs for clock generation and clock recovery

88E1111

Abstract: Marvell PHY 88E1111 Datasheet HFJ11-1G02E VSC8240 Marvell PHY 88E1111 altera Marvell PHY 88E1111 layout PC28F00AM29EWL Marvell PHY 88E1111 MDIO read write sfp 88e1111 sfp i2c Marvell PHY 88E1111 MDIO read write
Contextual Info: 100G Development Kit, Stratix IV GT Edition Reference Manual 100G Development Kit, Stratix IV GT Edition Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01057-1.0 Subscribe 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

S1221 AMCC

Abstract: Amcc S1221 ocp sfp SCP6802 SCP6802-GL TRPN03 HFBR-5908E S1201 S1202 S1204
Contextual Info: PRODUC T BRIEF S122 1 S1221 OC-3/12 SONET/SDH 8-bit Quad Transceiver Features Description • CMOS 0.13 micron technology • Complies with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation • On-chip high-frequency PLLs for clock generation and clock recovery

UG347

Abstract: Tianma TM162VBA6 TM162VBA6 ML507 Reference Design User Guide ML50x ML507 JS28F256P30T95 Marvell PHY 88E1111 ml505 Marvell 88E1111 trace layout guidelines Piezo speaker crossover
Contextual Info: ML505/ML506/ML507 ML505/ML506/M L507 Evaluation Evaluation Platform Platform User Guide [optional] UG347 v3.1.2 May 16, 2011 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

Tianma TM162VBA6

Abstract: TM162VBA6 88E1111 Marvell PHY 88E1111 alaska hard disk SATA pcb schematic ML507 JS28F256P30T95 tianma lcd graphic display HFJ11-1G01E AD1981 Codec
Contextual Info: ML505/ML506/ML507 ML505/ML506/M L507 Evaluation Evaluation Platform Platform User Guide [optional] UG347 v3.1 November 10, 2008 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

alaska atx 250 p4

Abstract: DSP48A1 SP605
Contextual Info: SP605 Hardware User Guide UG526 v1.8 September 24, 2012 Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

ET1081

Abstract: ET1011 ET1310 ET2005-50 ET5028-50 ET3028-50 agere et2008 ET2008
Contextual Info: Product Brief February 2006 ET5028-50 Single-Chip 28 x 1 Gbit/s Layer 2/3 Ethernet Switch Q Q Q Q Q Features Q Q Twenty-eight 10/100/1000 Mbits/s Ethernet ports: — Twenty-four-port, 6-pin SGMII interfaces to GbE copper PHYs — Four combo ports supporting either SGMII interface or

ET5028-50

Abstract: et1310 switch SGMII
Contextual Info: Product Brief February 2006 ET5048-50 Single-Chip 48 x 1 Gbit/s Layer 2/3 Ethernet Switch Q Q Q Q Q Features Q Q Forty-eight 10/100/1000 Mbits/s Ethernet ports: — Forty-four-port, 6-pin SGMII interfaces to GbE copper PHYs — Four combo ports supporting either SGMII interface or

XR2206 application notes

Abstract: pin diagram of ic xr2206 IC XR2206 XR2206 XR2206 pin details for function generator XR2206 monolithic function generator xr2206 circuit peb1756ae fsk modulation and demodulation using Xr2206 MXP2
Contextual Info: Communications OTN Multi-Service OTN Muxponder/Mapper Ethernet Transport Ethernet over PDH Ethernet over SONET/SDH PDH over SONET/SDH Port Expanders SONET/SDH Multi-Ch/Multi-Rate Framer+Serdes Mappers + Framers Transceivers/CDR PDH E1 LIUs T1/E1/J1 LIUs BITS Solutions