SERDES IP Search Results

Contextual Info: SERDES Evaluation Kit DS90UR241/124 USB Version 0.1 User Manual SERDES Demonstration Kit User Manual Rev 0.2 NSID: SERDESUR-43USB National Semiconductor Corporation Date: 5/8/2008 Page 1 of 36 SERDES Evaluation Kit DS90UR241/124 USB Version 0.1 User Manual

Mini USB 5Pin

Abstract: VG-835 50-pin lcd connector pinout Astro mini USB B 5pin panel mount banana jack DIN11 DS99R103 DS99R104 SERDES03-40USB
Contextual Info: SERDES Evaluation Kit DS99R103/104 USB Version 0.1 Users Manual SERDES Demonstration Kit User Manual NSID: SERDES03-40USB DS99R103/104 Rev 0.1 National Semiconductor Corporation Date: 5/14/2008 Page 1 of 38 SERDES Evaluation Kit DS99R103/104 USB Version 0.1 Users Manual

HDMP-2634

Abstract: 70841A C0603X7R160-104KNE CB10 E1 to fiber optic converter circuit
Contextual Info: Agilent HDMP-2634 2.5/1.25 GBd Serdes Circuit Data Sheet Description This data sheet describes the HDMP-2634 Serdes device for 2.5 GBd serial data rates. The HDMP-2634 Serdes is a silicon bipolar integrated circuit in a metallized QFP package. It provides a

lvds pin-out

Abstract: LVDS connector 30 pins LCD 50-pin lcd connector pinout lvds 40 pin pinout DS90UR241 nissei capacitors "3528-21" footprint lvds pinout MINI Jack 4PIN VG-835
Contextual Info: SERDES Evaluation Kit DS90UR241/124 USB Version 0.1 User Manual SERDES Demonstration Kit User Manual Rev 0.2 NSID: SERDESUR-43USB National Semiconductor Corporation Date: 5/8/2008 Page 1 of 36 SERDES Evaluation Kit DS90UR241/124 USB Version 0.1 User Manual

laser diode spice model simulation

Contextual Info: Agilent EEsof EDA W1714 SystemVue AMI Modeling Kit W1713 SystemVue SerDes Model Library Data Sheet Agilent’s W1714 SystemVue AMI Modeling Kit consists of SerDes libraries for SystemVue plus automatic IBIS AMI model generation. The W1713 SystemVue SerDes Model Library is a subset of W1714 that omits its code generation feature. It is used for architecture optimization of a serializer/deserializer SerDes

ispClock5406

Abstract: AN6081 SG-710ECK ispClock5400 SG-71 ispCLOCK5406D
Contextual Info: Driving SERDES Devices with the ispClock5400D Differential Clock Buffer October 2009 Application Note AN6081 Introduction In this application note we focus on how the ispClock 5406D and a low-cost CMOS oscillator can be utilized to drive the reference clock for SERDES-based applications. SERDES applications require accurate and low-jitter

Contextual Info: ispLever CORE TM SERDES Framer Interface Level 5 SFI-5 IP Core User’s Guide November 2008 ipug78_01.0 Lattice Semiconductor SFI-5 IP Core Introduction This document provides technical information about the Lattice SERDES Framer Interface Level 5 (SFI-5) IP core

Contextual Info: VSC8221 Data Sheet 1 GENERAL DESCRIPTION Ideally suited for Ethernet Switches with SGMII/SerDes MAC Interfaces, Media Converter applications, and SFP/GBIC modules, the industry-leading, low-power VSC8221 from Vitesse integrates a high-performance 1.25Gbps SerDes and

obsai

Abstract: Serdes IEEE standard 424M 802.3-2005
Contextual Info: High-Speed SERDES Interfaces In High Value FPGAs A Lattice Semiconductor White Paper February 2009 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: 503 268-8000 www.latticesemi.com 1 High-Speed SERDES Interfaces in High Value FPGAs

SY 351/6

Abstract: HP8656B service manual PWB 826 service manual PS 224 CITS25 DXSN2112 pj 939 PS-224 2 X 2 DUAL CROSSPOINT SWITCH amcc 10G palce programming algorithm
Contextual Info: SERDES Handbook April 2003 Dear Valued Customer, Lattice Semiconductor is pleased to provide you this second edition of our SERDES Handbook. Since offering the initial version last year, we have introduced several new products based on our superior sysHSI technology:

GDX2

Abstract: LX64EV-3F100C
Contextual Info: ispGDX2 Family Includes High, Performance t os -C w Lo “E” Series July 2004 Features • High Performance Bus Switching Preliminary Data Sheet ■ Two Options Available • High bandwidth – Up to 12.8 Gbps SERDES – Up to 38 Gbps (without SERDES)

Contextual Info: ispGDX2 Family Includes High, Performance t os -C w Lo “E” Series July 2004 Features • High Performance Bus Switching Preliminary Data Sheet ■ Two Options Available • High bandwidth – Up to 12.8 Gbps SERDES – Up to 38 Gbps (without SERDES)

RX5va

Abstract: FGND alcatel tributary card I-64 OC192 STM-64 i642 Alcatel optical transceiver STM 1 OIF99 alcatel PIN detector 10 Gbit
Contextual Info: Alcatel 1964 TRX SDH / SONET integrated modules SERDES Transceiver Transponder STM-64 / OC-192 Description These SERDES Transceivers are intended to be used at 10 Gbit/s optical SDH and SONET bit rate and provide electrical accesses at lower 622 Mbit/s bit rate. The modules are

vhdl code for stm-1 sequence

Abstract: TN1176 CDRPLL HB100 hd-SDI driver 424M encoder 74175 HD-SDI deserializer 16 bit parallel serdes Buffer QD004
Contextual Info: LatticeECP3 SERDES/PCS Usage Guide June 2010 Technical Note TN1176 Introduction The LatticeECP3 FPGA family combines a high-performance FPGA fabric, high-performance I/Os and up to 16 channels of embedded SERDES with associated Physical Coding Sublayer PCS logic. The PCS logic can be

Contextual Info: Whpl HEW LETT mLUMPACKARD Gigabit Ethernet SerDes Circuit w ith Differential PE CL Clock Inputs HDMP-1637A SerDes Features • IEEE 802.3z Gigabit Ethernet Compatible, Supports 1250 MBd Gigabit Ethernet • Based on X3T11 “10 Bit Specification” • Low Power Consumption

hp 2631

Abstract: HP 2630 A 2631 hp 2630 datasheet C0603X7R160-104KNE HDMP-2630 A 2631 line receiver HDMP-2631 A 2630 RX-2 -G s
Contextual Info: Agilent HDMP-2630/2631 2.125/1.0625 GBd Serdes Circuits Data Sheet Description This data sheet describes the HDMP-2630/2631 serdes devices for 2.125 GBd serial data rates. References to SSTL_2 in the text will also apply to SSTL_3; however, there are separate tables and figures

32F2

Abstract: TN1003
Contextual Info: ispGDX2 Family Includes High, Performance t os -C w Lo “E-Series” July 2004 Features • High Performance Bus Switching Preliminary Data Sheet ■ Two Options Available • High bandwidth – Up to 12.8 Gbps SERDES – Up to 38 Gbps (without SERDES)

VSC8221XHH

Abstract: VSC8221hh vsc8221 yx 805 led driver VSC8211 741 IC data sheet 5555D hybrid MDI RGMII to SGMII PHY sgmii
Contextual Info: VSC8221 Data Sheet Single-Port 10/100/1000BASE-T PHY with 1.25 Gbps SerDes for SFPs/GBICs 1 GENERAL DESCRIPTION Ideally suited for Ethernet Switches with SGMII/SerDes MAC Interfaces, Media Converter applications, and SFP/GBIC modules, the industry-leading, low-power VSC8221 from

verilog code of prbs pattern generator

Abstract: verilog code 16 bit LFSR in PRBS prbs using lfsr verilog prbs generator LFE2M50E prbs generator
Contextual Info: LatticeECP2M PRBS SERDES Demo User’s Guide June 2010 Technical Note TN1153 Introduction This demo illustrates the SERDES/PCS abilities of the LatticeECP2M FPGA family. It does this by embedding a simple pseudo-random pattern into an 8b10b-encoded PCS payload, then looping back the payload, and checking

verilog prbs generator

Abstract: verilog code of prbs pattern generator verilog code 16 bit LFSR in PRBS fpga loader ECP2M LFE2M50E TN1124 prbs generator ISPVM
Contextual Info: LatticeECP2M PRBS SERDES Demo User’s Guide August 2009 Technical Note TN1153 Introduction This demo illustrates the SERDES/PCS abilities of the LatticeECP2M FPGA family. It does this by embedding a simple pseudo-random pattern into an 8b10b-encoded PCS payload, then looping back the payload, and checking

OSERDES

Abstract: oserdes2 DDR spartan6 XAPP1064 ISERDES2 oserdes2 serdes clock_generator_ddr_s8_diff ISERDES spartan 6 SP601 Clock-Generator
Contextual Info: Application Note: Spartan-6 FPGAs Source-Synchronous Serialization and Deserialization up to 1050 Mb/s XAPP1064 (v1.0) December 23, 2009 Author: NIck Sawyer Summary Spartan -6 devices contain input SerDes (ISERDES) and output SerDes (OSERDES) blocks. These primitives simplify the design of serializing and deserializing circuits, while allowing

PM8358-NI

Abstract: M0330 196-pin bga footprint 10G serdes PM8358 CX4 connector PM8355 10G serdes 2.5 xaui wireles ethernet PM8354
Contextual Info: Signal Integrity There’s more than Meets the Eye PMC-Sierra’s Multi-Gigabit Serial Expertise • Core to PMC-Sierra Business • >65% of PMC products integrate SERDES • History delivering production hardened SERDES • Discrete and highly integrated products such as:

GR-1377-CORE

Abstract: Alcatel optical transceiver STM 1 alcatel transmitter Alcatel optical transceiver datasheet STM 1 I-64 STM-64 alcatel sdh tx alcatel PIN detector 10 Gbit Alcatel optical transmitter
Contextual Info: Alcatel 1964 TRX SDH / SONET integrated modules SERDES Transceiver STM-64 / OC-192 Description These SERDES Transceivers is intended to be used at 10 Gbit/s optical SDH and SONET bit rate and provide electrical accesses at lower 622 Mbit/s bit rate. The modules are housed in a

higig2

Contextual Info: BCM56802 16-PORT 10GBE/HIGIG2 MULTILAYER SWITCH SUMMARY OF BENEFITS FEATURES • Sixteen HiGig2 /HiGig™+/HiGig™/10-GbE/1-GbE ports • Based on StrataXGS™ field-proven, robust architecture • Integrated high-performance SerDes • Integrated XAUI™ SerDes for all 16 ports