SERDES HSIF Search Results

GDX2

Abstract: LX64EV-3F100C
Contextual Info: ispGDX2 Family Includes High, Performance t os -C w Lo “E” Series July 2004 Features • High Performance Bus Switching Preliminary Data Sheet ■ Two Options Available • High bandwidth – Up to 12.8 Gbps SERDES – Up to 38 Gbps (without SERDES)

Contextual Info: ispGDX2 Family Includes High, Performance t os -C w Lo “E” Series July 2004 Features • High Performance Bus Switching Preliminary Data Sheet ■ Two Options Available • High bandwidth – Up to 12.8 Gbps SERDES – Up to 38 Gbps (without SERDES)

32F2

Abstract: TN1003
Contextual Info: ispGDX2 Family Includes High, Performance t os -C w Lo “E-Series” July 2004 Features • High Performance Bus Switching Preliminary Data Sheet ■ Two Options Available • High bandwidth – Up to 12.8 Gbps SERDES – Up to 38 Gbps (without SERDES)

Contextual Info: ispGDX2V/B/C Family High Performance Interfacing and Switching October 2002 Preliminary Data Sheet Features • sysHSI Blocks Provide up to 16 High-Speed Channels – Serializer/de-serializer SERDES included – Clock Data Recovery (CDR) built in – 850 Mbps per channel

p543a

Abstract: p543-a P281B P452A N422A P483-A n70a N483A p765a TN1003
Contextual Info: ispGDX2V/B/C Family High Performance Interfacing and Switching September 2003 Preliminary Data Sheet Features • Programmable drive strength • sysHSI Blocks Provide up to 16 High-Speed Channels – Serializer/de-serializer SERDES included – Clock Data Recovery (CDR) built in

Contextual Info: ispGDX2 Family High Performance Interfacing and Switching June 2004 Preliminary Data Sheet Features • Programmable drive strength • sysHSI Blocks provide up to 16 high-speed channels – Serializer/de-serializer SERDES included – Clock Data Recovery (CDR) built in

36P3A

Abstract: TN1003 759P Tri-State Buffer CMOS
Contextual Info: ispGDX2V/B/C Family High Performance Interfacing and Switching March 2004 Preliminary Data Sheet Features • Programmable drive strength • sysHSI Blocks provide up to 16 high-speed channels – Serializer/de-serializer SERDES included – Clock Data Recovery (CDR) built in

8b/10b-Serializer Coding Example

Abstract: p452a TN1034 m20 thermal fuse 115 U1 V1 and W1 is delta connections TN1003 442A8 TN1000 p1086-a p281b
Contextual Info: ispGDX2V/B/C Family High Performance Interfacing and Switching May 2003 Preliminary Data Sheet Features • Programmable drive strength • sysHSI Blocks Provide up to 16 High-Speed Channels – Serializer/de-serializer SERDES included – Clock Data Recovery (CDR) built in

Contextual Info: ispGDX2 Family Includes High, Performance t os -C w Lo “E-Series” September 2004 Features Data Sheet • Two Options Available • High-performance sysHSI standard part number • Low-cost, no sysHSI (“E-Series”) ■ High Performance Bus Switching

lx64ev-3f100c

Abstract: LX64V-3F100C 3F100 5f208c LX64V-3FN100 LX64EB-5F100C LX128EV-5FN208I LX128EV-5FN208C LX64B-3FN100C LX64B-5F100C
Contextual Info: ispGDX2 Device Datasheet June 2010 Select Devices Discontinued! Product Change Notifications PCNs #09-10 has been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes.

LX128EV-5FN208C

Abstract: TN1003 759P
Contextual Info: ispGDX2 Family Includes High, Performance t os -C w Lo “E-Series” September 2005 Features Data Sheet • Two Options Available • High-performance sysHSI standard part number • Low-cost, no sysHSI (“E-Series”) ■ High Performance Bus Switching

8n9p

Abstract: TN1020 11GB
Contextual Info: ispGDX2 Family Includes High, Performance t os -C w Lo “E-Series” November 2004 Features Data Sheet • Two Options Available • High-performance sysHSI standard part number • Low-cost, no sysHSI (“E-Series”) ■ High Performance Bus Switching

12v inverter

Abstract: 90nm 90nm ROM Etch Microelectronics 90nm cmos CS101SN CS101 10-Layer CHIP IPS serdes hsif
Contextual Info: 90nm CMOS Standard Cell CS101 ASIC Series High-performance transistors • Advanced lithography and etch technology to achieve 40nm gate length • Low temperature process for shallow junction • Process optimization for high carrier mobility 9Cu/1Al interconnect

CS200

Abstract: 65nm DDR PHY ASIC HDMI to lvttl cmos logic 90nm DAC 90nm CS200A 65-NM UHS SD Card Hdmi to micro usb wiring
Contextual Info: 65nm CMOS Standard Cell Leakage Current Large CS200 ASIC Series Server/ Network Low Power Power Low Lineup Lineup CS200LL CS200A HV-Tr DHV-Tr HS-Tr Mo C Mobile STD-Tr STD-Tr LL-Tr Computing High End Server HighHigh Performance Performance Lineup LineupCS200HP