SDRAM DIMM 1997 Search Results

pc100-322-620

Abstract: SDA Physical Layer Specification Version 3.00 1MX16 2MX32 4MX16 SO DIMM DRAM 144 Pin Connector Pinout BA1A11
Contextual Info: PC SDRAM Unbuffered DIMM Specification PC SDRAM UNBUFFERED DIMM SPECIFICATION REVISION 0.9 Oct. 22, 1997 1 of 46 Revision 0.9 PC SDRAM Unbuffered DIMM Specification THIS DOCUMENT IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY

SO DIMM DRAM 144 Pin Connector Pinout

Abstract: SO DIMM 100 Pin Connector Pinout CB15 BA142
Contextual Info: cts. a h IC M A R D S rd fe u b U in P 8 6 1 168 Pin Unbuffered SDRAM DIMM Characteristics Basic Architecture SDRAM Addressing Effects The IBM 168 pin 8 Byte Unbuffered SDRAM DIMM is intended for personal computers and workstations using eight byte memory interfaces. These systems

Contextual Info: MOSEL VITELIC PRELIMINARY V436416S04VTG 3.3 VOLT 16M x 64 HIGH PERFORMANCE PC100AND 100 M HZ SDRAM UNBUFFERED DIMM Features Description • 168 Pin Unbuffered 16,777,216 x 64 bit Oganization SDRAM Modules ■ Utilizes High Performance 8M x 8 SDRAM in TSOPII-54 Packages

Contextual Info: MOSEL VITELIC PRELIMINARY V43728S04VTG 3.3 VOLT 8 M x 72 HIGH PERFORMANCE PC100AND 100 M HZ SDRAM UNBUFFERED DIMM Features Description • 168 Pin Unbuffered 8,388,608 x 72 bit Oganization SDRAM Modules ■ Utilizes High Performance 8M x 8 SDRAM in TSOPII-54 Packages

cs 2313

Contextual Info: M OSEL V I T E L I C V43728S04VTG 3.3 VOLT 8M x 72 HIGH PERFORMANCE PC100 AND 100 MHZ SDRAM UNBUFFERED DIMM PRELIMINARY Features Description • 168 Pin Unbuffered 8,388,608 x 72 bit Oganization SDRAM Modules ■ Utilizes High Performance 8M x 8 SDRAM in TSOPII-54 Packages

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT MC-454CB64S 4M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM Description The MC-454CB64S is a 4,194,304 words by 64 bits synchronous dynam ic RAM module (Small Outline DIMM) on which 4 pieces of 64 M SDRAM: ^¡PD4564163 are assembled.

Contextual Info: DATA SHEET_ MOS INTEGRATED CIRCUIT MC-452AB64S 2 M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM Description The MC-452AB64S is a 2,097,152 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on which 8 pieces of 16M SDRAM: ,uPD4516821 A are assembled.

Contextual Info: IBM13T2649NC 2M x 64 2 Bank SDRAM SO DIMM Features 144 Pin emerging JEDEC Standard, 8 Byte Small Outline Dual-In-line Memory Module 2M x64 Synchronous DRAM SO DIMM Performance: 10 CAS Latency ; 12 Units 3 3 fcK Clock Frequency tcK Clock Cycle 100 : 83 10

HB526C464EN-10IN

Abstract: Hitachi DSA00164 Nippon capacitors
Contextual Info: HB526C264EN-10IN, HB526C464EN-10IN 16/32 MB Unbuffered SDRAM DIMM 2-M/4-Mword x 64-bit, 66 MHz Memory Bus, 1/2-Bank Module 8/16 pcs of 2 M × 8 Components ADE-203-737D (Z) Rev. 4.0 Nov. 1997 Description The HB526C264EN, HB526C464EN belong to 8-byte DIMM (Dual In-line Memory Module) family, and

Contextual Info: IBM13N2649JC IBM13N2739JC 2M x 64/72 1 Bank Unbuffered SDRAM Module Features • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-line Memory Module • 2Mx64/72 Synchronous DRAM DIMM • Performance: 10 CAS Latency jfc K I Clock Frequency ItcK i Clock Cycle

Contextual Info: IBM13Q8739CC 8M x 72 Buffered SDRAM Module Features • 200-Pin emerging JEDEC Standard, Buffered 8Byte Dual In-line Memory Module • 8M x 72 Synchronous DRAM DIMM • Performance: CAS Latency = 2* -10 j Units j ! MHz j ; ns jfcK j Clock Frequency 66 ; tcK2

Contextual Info: IBM13N1649NC IBM13N1809NC 1M x 64/80 1 Bank Unbuffered SDRAM Module Features • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-line Memory Module • 1 Mx64/80 Synchronous DRAM DIMM • Performance: CAS Latency • • • • • • -10 3 jfc K Clock Frequency

Contextual Info: IBM13N8739CC 8M x 72 2 Bank Unbuffered SDRAM Module Features • 168 Pin Unbuffered 8 Byte Dual In-line Memory Module • 8Mx72 Synchronous DRAM DIMM • Performance: j 10 j Units! CAS Latency 3 ! fcK I Clock Frequency jtcK j Clock Cycle iUc j Clock Access Time j

Contextual Info: IBM13Q4739CC 4M x 72 Registered SDRAM Module Features • Programmable Operation: • 200-Pin emerging JEDEC Standard, Buffered 8Byte Dual In-line Memory Module • 4M x 72 Synchronous DRAM DIMM • Performance: -10 : U nits j ! fcK j C lo c k F re q u e n c y

Nippon capacitors

Abstract: 0/B526C464EN
Contextual Info: HB526C264EN-10IN, HB526C464EN-10IN 16/32 MB Unbuffered SDRAM DIMM 2-M/4-Mword x 64-bit, 66 MHz Memory Bus, 1/2-Bank Module 8/16 pcs of 2 M x 8 Components HITACHI ADE-203-737D (Z) Rev. 4.0 Nov. 1997 Description The H B526C264EN , H B526C 464EN belong to 8-byte D IM M (D ual In-line M em ory M odule) fam ily, and

Contextual Info: IB M 1 3 T 1 6 4 9 N C 1M x 64 1 Bank SDRAM SO DIMM Features • 144 Pin em erging JE D E C S tandard, 8 Byte Sm all O utlin e D u al-In -lin e M em o ry M odule • P rog ram m a ble O peration: -C A S Latency: 1, 2, 3 • 1 M x64 S ynch ron ou s DR AM SO DIM M

Contextual Info: TM8SR64JPU, TM16SR64JPU TM8SR72JPU, TM16SR72JPU SYNCHRONOUS DYNAMIC RAM MODULES SMMS688 - AUGUST 1997 Organization: - TM8SR64JPU . . . .8 388 608 x 64 Bits - TM16SR64JPU . . 16 777 216 x 64 Bits - TM8SR72JPU . . . .8 388 608 x 72 Bits - TM16SR72JPU . . 16 777 216 x 72 Bits

TMS626812

Contextual Info: TM2SR72EPN 2097152 BY 72-BIT TM4SR72EPN 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES S M M S 698A -JU N E 1997-R E V IS E D FEBRUARY 1998 Organization - TM2SR72EPN . . . 2097152 x 72 Bits - TM4SR72EPN . . .4194304 x 72 Bits High-Speed, Low-Noise Low-Voltage TTL

Contextual Info: July 1997 Revision 1.0 data sheet SDC4UL7284- 67/84/100 T-S 32MByte (4M x 72) CMOS Synchronous DRAM Module - ECC General Description The SDC4UL7284-(67/84/100)T-S is a high performance, 32-megabyte synchronous, dynamic RAM module organized as 4M words by 72 bits, in a 168-pin, JEDEC ECC configuration, dual-in-line memory module (DIMM) package.

106E capacitor

Contextual Info: June 1997 Revision 1.1 data sheet SDC4UV7282C- 67/84/100/125 T-S 32MByte (4M x 72) CMOS Synchronous DRAM Module - ECC General Description The SDC4UV7282C-(67/84/100/125)T-S is a high performance, 32-megabtye synchronous, dynamic RAM module organized as 4M words by 72 bits, in a 168-pin, JEDEC ECC configuration, dual-in-line memory module (DIMM) package.

Contextual Info: Dec. 1997 Revision 2.0 data sheet SDC8UL7284- 67/84/100/125 T-S 64MByte (8M x 72) CMOS Synchronous DRAM Module General Description The SDC8UL7284-(67/84/100/125)T-S is a high performance, 64-megabyte synchronous, dynamic RAM module organized as 8M words by 72 bits, in a 168-pin, dual-in-line memory module (DIMM) package.

Contextual Info: cP ÍITSU IJ L 1 J v May 1997 Revision 1.0 d a ta s h e e t SDC8UV7284- 67/84/100/125 T-S 64MByte (8M x 72) CMOS Synchronous DRAM Module General Description The SDC8UV7284-(67/84/100/125)T-S is a high performance, 64-megabtye synchronous, dynamic RAM module organized as

SDRAM DIMM 1997

Contextual Info: December 1997 Revision 1.0 data sheet PDC4UV7284A- 75/102/103 T-S 32MByte (4M x 72) CMOS, PC/100 Synchronous DRAM Module - ECC General Description The PDC4UV7284A-(75/102/103)T-S is a high performance, 32-megabyte synchronous, dynamic RAM module organized as 4M

Contextual Info: cP IITSU June 1997 Revision 1.1 data sheet SDC4 U V7282C- 67/84/100/125 T-S 32MByte (4M x 72) CMOS Synchronous DRAM Module - ECC General Description The SDC4UV7282C-(67/84/100/125)T-S is a high performance, 32-megabtye synchronous, dynamic RAM module organized as