SCBD002 Search Results

A1619A

Abstract: b1241
Contextual Info: SN54ABT32318, SN74ABT32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS SCBS180A-JUNE 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus+ Family State-of-the-Art EPIC-IlB™ BICMOS Design Significantly Reduces Power Dissipation Typical V q l p Output Ground Bounce

Contextual Info: SN74CBT3386 10-BIT BUS-EXCHANGE SWITCH WITH EXTENDED VOLTAGE RANGE SCDS022 - MAY 1995 DB, DW, OR PW PACKAGE TOP VIEW BE [ 1 U [ 2 [ 3 [ 4 [ 5 [ 6 [ 7 [ 8 [ 9 [ 10 [ 11 VDD [ 12 1B1 1A1 1A2 1B2 2B1 2A1 2A2 2B2 3B1 3A1 description The SN74CBT3386 provides ten bits of

Contextual Info: SCDS002C - NOVEMBER 1992 - REVISED MAY 1995 DB, DW, OR PW PACKAGE TOP VIEW Functionally Equivalent to QS3245 Standard '245-Type Pinout 5-iî Switch Connection Between Two Ports NC [ 1 A1 [ 2 TTL-Compatible Control Input Levels A2 [ 3 A3 [ 4 A4 [ 5 Package Options Include Shrink

Contextual Info: SN74CBT3257 QUADRUPLE 2-BIT TO 1-BIT FET MULTIPLEXER/DEMULTIPLEXER SCDS017-MAY 1995 I • • • • S[ 1 1B1 [ 2 1B2 [ 3 1A [ 4 description The SN74CBT3257 is a quadruple 2-bit to 1-bit high-speed TTL-compatible FET multiplexer/ demultiplexer. The low on-state resistance of the

Contextual Info: SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 3CAS317A- NOVEMBER 1993 - REVISED OCTOBER 199S | • Member of the Texas Instruments Wldobua Family • EP/C™ Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce)

Contextual Info: SN74LVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCAS279B-JANUARY 1993 - REVISED JULY 1995 I • EP/C Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MII-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74LVC157 QUADRUPLE 2-LINE TO 1-UNE DATA SELECTOR/MULTIPLEXER SCAS292B-JANUARY 19 9 3 - REVISED JULY 1995 I • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model

Contextual Info: CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS _ SCAS335A-DECEMBER 1992-R E V IS E D NOVEMBER 1995 D PACKAGE TOP VIEW Low Output Skew for Clock-Distribution and Clock-Generatlon Applications

Contextual Info: SN74LVC827 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS306B - MARCH 1993 - REVISED JULY 1996 • EPIC Enhanced-Performance Implanted CMOS Submicron Process db , dw , o r pw packaqe (t o p v ie w ) Typical Vqlp (Output Ground Bounce) < 0.8 V at Vcc = 3-3 V, TA = 25'C

Contextual Info: SN74LVC863 9-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS31OA - M A RCH 1993 - REVISED JULY 1996 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce) < 0.8 V at Vcc = 3.3 V, TA = 25°C | DB, DW, OR PW PACKAQE

74ABTH18646A

Contextual Info: SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS SCBS166D - AUGUST 1993 - REVISED JULY 1996 Members of the Texas Instruments SCOPE Family of Testability Products One Boundary-Scan Cell Per I/O

SN74LVC162244

Contextual Info: SN74LVC162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS I SCAS546 - OCTOBER 1995 10Ê 1Y1 1Y2 GND 1Y3 1Y4 Output Ports Have Equivalent 26-Q Series Resistors, So No External Resistors Are Required Typical V q l p Output Ground Bounce < 0.8 V at Vc c = 3.3 V, TA = 25°C

Contextual Info: SN74LVCU04 HEX INVERTER SCAS282B - JANUARY 1993 - REVISED JULY 1995 D, DB, OR PW PACKAGE TOP VIEW • EP/C (Enhanced-Performance Implanted CMOS) Submicron Process I • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _SCAS337B- FEBRUARY 1 9 9 3 - REVISED NOVEMBER 1996 * f • • • • • • Low Output Skew for Clock-Dlstrlbutlon and Clock-Generation Applications Operates at 3.3-V Vqc Distributes One Clock Input to IWelve

Contextual Info: SN74LVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS 3CES081A - DECEMBER 1 9 95 - REVISED JANUARY 1998 DQQ OR DL PACKAOE TOP VIEW Member of the Texas Instruments Wldebus Family EP/C™ (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce)

CDC2510A

Contextual Info: CDC2510A 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS604A– APRIL 1998 – REVISED JUNE 1998 D D D D D D D D D D PW PACKAGE TOP VIEW Spread Spectrum Clock Compatible 100 MHz Maximum Frequency Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for

Contextual Info: SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 • • • • • • State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per

Contextual Info: CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve

Contextual Info: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442C – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve

BCT8373A

Contextual Info: SN54BCT8373A, SN74BCT8373A SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES SCBS044F – JUNE 1990 – REVISED JULY 1996 D D D D D description The ’BCT8373A scan test devices with octal D-type latches are members of the Texas Instruments SCOPE testability integratedcircuit family. This family of devices supports IEEE

Contextual Info: CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit

CDC9842

Contextual Info: CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS SCAS546B – NOVEMBER 1995 – REVISED MAY 1996 D D D D D D D D D D Provides System Clock Solution for Pentium/82430X/82430VX and PentiumPro 82440FX Chipsets Four Host-Clock Outputs With

Contextual Info: SN54ABT374, SN74ABT374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS111D – FEBRUARY 1991 – REVISED JULY 1994 • • • • State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA