SAN ACE 80 32 Search Results

Contextual Info: • LOW VOLTAGE 23000 Series ROMS IMP23LV128 IMP23LV100 IMP23LV256 IMP23LV101 IMP23LV512 IMP23LV208 LOW VOLTAGE/HIGH PERFORMANCE CMOS ROMS Features • Six JEDEC Standard Versions: IMP23LV128 IMP23LV256 IMP23LV512 IMP23LV100 IMP23LV101 IMP23LV208 28 28 28

San Ace 40

Abstract: 109p0412 109P0412K3013 San Ace 40 12v 109P0405H301 109P0405H3013 109P0424H301 San Ace 40 24v 109p0424h3 109P0412B3013
Contextual Info: DC Fan 40 San Ace 40 10mm thick, 15mm thick, 20mm thick 28mm thick GE type 28mm thick (GV type), 28mm thick mm sq. • General Specifications With a pulse sensor Specifications for pulse sensors Refer to Page 261 ・Material …………………… Frame: Plastics (Flammability: UL94V-0),

Contextual Info: MAY 4 1992 w .- . IMP23L128 IMP23L256 IMP23L512 VERY LOW POWER 23000 Series ROMS IMP23L100 IMP23L101 IMP23L208 LOW POWER/HIGH PERFORMANCE CMOS ROMS Features • Six JEDEC Standard Versions: IMP23L128 IMP23L256 IMP23L512 IMP23L100 IMP23L101 IMP23L208

Contextual Info: High Performance 32Kx8 CMOS SRAM p i AS7C256 AS7C256L 32Kx8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words x 8 bits Equal access and cycle times • High speed Easy memory expansion with CE and OE inputs - 10/12/15/20/25/35 ns address access time

Contextual Info: V62C3162096L L Ultra Low Power 128K x 16 CMOS SRAM Features Functional Description • Ultra Low-power consumption - Active: 65mA ICC at 35ns - Stand-by: 10 µA (CMOS input/output) 2 µA (CMOS input/output, L version) The V62C3162096L is a Low Power CMOS Static

Contextual Info: HITACHI/ MCU/MPU ^2 I>e | 44TL204 □ Q l E 3 0 b 5 -4TÔ6 2 Ö 4 H 1 iACH i / M C U /M P U 92D 12306 dH HD63085-—-—T-53-333bDI CEP Document Image Compression and Expansion Processor PRELIM INARY- The HD63085 (DICEP) is a LSI th a t compresses (or encodes)

uart 550c Texas Instruments

Contextual Info: TL16C554A, TL16C554AI ASYNCHRONOUSĆCOMMUNICATIONS ELEMENT ą ąą SLLS509B − AUGUST 2001 − REVISED AUGUST 2005 D Integrated Asynchronous-Communications D D D D D D D D Element Consists of Four Improved TL16C550C ACEs Plus Steering Logic In FIFO Mode, Each ACE Transmitter and

EEPROM I2C atmel

Abstract: alarm clock verilog code atmel dac adc
Contextual Info: I NTEGRATION S YSTEM L EVEL AVR EMBEDDED MICROCONTROLLER RO Flash M or Pro Mem gram ory CORE SYSTEM JTAG Port Prog r Down am load Ser Perip ial h Interf eral ace EEPR Refe OM renc Data e R E On-c hip Debu g O C Syste mC Sour lock PLL, ce: OSC R AV Up to 60 MIPS at 70

A14C

Abstract: CY7C1020V
Contextual Info: fax id: 1075 : : : : : jT ^ ik n S t^ r ^ h t* P R E L IM IN A R Y C Y7C 1020V 32K x 16 Static RAM Features BLE is LOW, then da ta from I/O pins (l/O-j throu gh l/ 0 8), is w ritten into the location specified on th e address pins (A 0 throu gh A-| 4 ). If byte high en ab le (BH E) is LOW, then da ta from

camera-link to hd-SDI converter

Abstract: Virtex-4QV DS-KIT-FX12MM1-G AES-S6DEV-LX150T-G VHDL code for ADC and DAC SPI with FPGA spartan 3 ADQ0007 XC6SL AES-XLX-V4FX-PCIE100-G SPARTAN-3 XC3S400 based MXS3FK ADS-XLX-SP3-EVL400
Contextual Info: Product Selection Guides Table of Contents February 2010 Virtex Series . 2 Spartan Series . 6

Contextual Info: fax id: 1030 CY7C199 32K x 8 Static RAM Features provided by an active LOW chip enable CE and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consum p­ tion by 81% when deselected. The C Y7C 199 is in the standard

MAX6326_R22-T

Abstract: FPAA application in MAX6326 MAX6328 MAX6348 marking package acw MAX6327R31-T MAX6326-R22-T maxim TOP MARKING
Contextual Info: 19-1294; Rev 4; 12/05 3-Pin, Ultra-Low-Power SC70/SOT µP Reset Circuits The MAX6326/MAX6327/MAX6328/MAX6346/MAX6347/ MAX6348 microprocessor µP supervisory circuits monitor the power supplies in µP and digital systems. These devices provide excellent circuit reliability and low cost

130539

Abstract: END55 25Z-12
Contextual Info: CYK001M16SCCAU MoBL ADVANCE INFORMATION 16-Mb 1M x 16 Pseudo Static RAM Features • Advanced low power MoBL architecture • High speed: 70 ns • Wide voltage range: — VCC range: 2.7V to 3.3V • Low active power — Typical active current: 2 mA @ f = 1 MHz

CY7C028-15AI

Abstract: WH15 CY7C027 CY7C028 CY7C037 CY7C038 IDT7027
Contextual Info: CY7C027/028 CY7C037/038 PRELIMINARY 32K/64K x 16/18 Dual-Port Static RAM Fully asynchronous operation Automatic power-down Expandable data bus to 32/36 bits or more using Mas­ ter/Slave chip select when using more than one device On-chip arbitration logic

Contextual Info: fax id: 5206 W CYPRESS CY7C024/0241 CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description True Dual-Ported memory cells which allow simultaneous reads of the same mem ory location 4K x 16 organization CY7C024

fire hydrant

Abstract: HYDRAN utility diversion meters power reports "variable frequency drive" circuit Philips LED 1972 utility diversion meters power chilled water system AMD product line foot step generation of electricity
Contextual Info: AMD Environmental, Health and Safety Annual Report 1998 To Our Stakeholders Great companies are defined by their core values. For more than 30 years, AMD has been guided by one simple belief: People first. Products and profits will follow. All of our business practices are derived from

Contextual Info: W jÊ CY7C024AV/025AV/026AV CY7C0241 AV/0251 AV/036AV PRELIMINARY 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Features • True dual-ported m em ory cells which allow sim ulta­ neous access of the same m em ory location • 4/8/16K x 16 organization CY7C024AV/025AV/026AV

ML-02-L

Abstract: d1645
Contextual Info: fax id: 5212 CYPRESS C Y 7 C 1 3 8 V /1 4 4 V /0 0 6 V /0 0 7 V PRELIMINARY C Y 7 C 1 3 9 V /1 4 5 V /0 1 6 V /0 1 7 V 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM A u to m atic pow er-dow n Features E xp a n d ab le d ata bus to 16 /18 bits o r m o re using M as ter/

CY62148

Abstract: CY62148-55 CY62148-70SC CY62148-70ZSC CY62148L-70SC CY62148L-70ZSC ZS32
Contextual Info: fax id: 1079 w CY62148 PRELIMINARY / C Y P R E S S 51 2 Kx 8 Features Static RAM an au tom atic pow er-dow n feature th a t reduces pow er co n ­ sum p tion by m ore tha n 99 % w h en deselected. • 4 .5 V -5 .5 V o peratio n W riting to th e device is accom plished by takin g chip enable

Contextual Info: fax id: 5214 CYPRESS CY7C008V/009V CY7C018V/019V PRELIMINARY 3.3V 64K/128K x 8/9 Dual-Port Static RAM Features True Dual-Ported mem ory cells which allow sim ulta­ neous access of the same mem ory location 64K x 8 organization CY7C008 128K x 8 organization (CY7C009)

TH4B

Contextual Info: PHAST-3N STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 DATA SHEET • • • • • • • • • • • • • • • • • Bit-serial SDH/SONET line interface - Pseudo-ECL interface with clock recovery and synthesis

tms70c20

Abstract: tms70c00 TMS7000 TMS7000 instruction set TMS7001 TMS7020 TMS70C40 NGK Spark Plug TMS7000 development system TMS7000 Family Data Manual
Contextual Info: ELECTRICAL SPECIFICATIONS 4. 4 .1 T M S 7 0 0 0 /T M S 7 0 2 0 /T M S 7 0 4 0 /T M S 7 0 1 2 0 /T M S 7 0 0 1 /T M S 7 0 4 1 4 .1 .1 Description O f The T M S 7 0 0 0 /T M S 7 0 2 0 /T M S 7 0 4 0 /T M S 7 0 1 2 0 /T M S 7 0 0 1 /T M S 7 0 4 1 The T M S 7 0 X 0 d evices T M S 7 0 0 0 , T M S 7 0 2 0 , T M S 7 0 4 0 , and T M S 7 0 1 2 0 are single chip

JK60

Abstract: A13L CY7C026 CY7C036 IDT70261
Contextual Info: fax id: 5223 CYPRESS CY7C026 CY7C036 PRELIMINARY 16K x 16/18 Dual-Port Static RAM A u to m atic pow er-dow n Features • True D u al-P o rted m e m o ry cells w h ich allo w sim u lta­ n eo us ac c e s s o f th e s a m e m e m o ry location • 16K x 16 o rg an iza tio n C Y 7C 026

CY7C007

Abstract: CY7C007-12JC CY7C017 IDT7007
Contextual Info: fax id: 5222 CYPRESS CY7C007 CY7C017 PRELIMINARY 3 2 K x 8/9 Dual-Port Static RAM Fully a s yn ch ro n o u s o peratio n Features A u to m atic pow er-dow n • True D u al-P o rted m e m o ry cells w h ich allo w sim u lta­ n eo us ac c e s s o f th e s a m e m e m o ry location