SA 101 1E M Search Results

Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS SA 7mmL, For General Purposes series Standard miniature series with 7mm height. SR 7mmL, High CV series Smaller SR series Higher CV series with 7mm ST height. High Temperature Adapted to the RoHS directive (2002/95/EC). SL

MARKING SR

Abstract: SR SERIES electrolytic capacitors
Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS SA 7mmL, For General Purposes series Standard miniature series with 7mm height. SR 7mmL, High CV series Smaller SR series ST Higher CV series with 7mm height. High Temperature SP Bi-polarized SL Low Leakage Current SA Smaller

D 44 SR

Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS SA 7mmL, For General Purposes series Standard miniature series with 7mm height. SR 7mmL, High CV series Smaller SR series Higher CV series with 7mm height. ST High Temperature SP Bi-polarized SL Low Leakage Current SA Smaller

Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS SA SR 7mmL, For General Purposes series Standard miniature series with 7mm height. 7mmL, High CV series Smaller SR series Higher CV series with 7mm ST height. High Temperature Compliant to the RoHS directive (2002/95/EC).

Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS SA SR 7mmL, For General Purposes series Standard miniature series with 7mm height. 7mmL, High CV series Smaller SR series Higher CV series with 7mm ST height. High Temperature Adapted to the RoHS directive (2002/95/EC). SA

SA SERIES electrolytic capacitors

Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS SA SR 7mmL, For General Purposes series Standard miniature series with 7mm height. 7mmL, High CV series Smaller SR series Higher CV series with 7mm ST height. High Temperature Adapted to the RoHS directive (2002/95/EC). SL

Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS SA 7mmL, For General Purposes series Standard miniature series with 7mm height. SR 7mmL, High CV series Smaller SR series Higher CV series with 7mm ST height. High Temperature SL SA Low Leakage Current SP Bi-polarized Smaller

Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS SA SR 7mmL, For General Purposes series Standard miniature series with 7mm height. 7mmL, High CV series Smaller SR series Higher CV series with 7mm ST height. High Temperature Compliant to the RoHS directive (2002/95/EC).

Contextual Info: ALUMINUM ELECTROLYTIC CAPACITORS SA 7mmL, For General Purposes series Standard miniature series with 7mm height. SR 7mmL, High CV series Smaller SR series Higher CV series with 7mm ST height. High Temperature Adapted to the RoHS directive (2002/95/EC). SL

z5u .05

Abstract: Z5U diode capacitor 104 100v 100pf Capacitor dimension 10pf Capacitor dimension 10pf npo 12 PIN SIP 11-pin CAPACITOR z j k voltage 100PF
Contextual Info: Capacitor Networks-sip RATING E-12 Series Capacitance Range CS 10pf-0.022µF 0.01µF-1µF T.C.R. NPO, X7R, Z5U Capacitance Tol. DIMENSION：mm CL J, K, M, Z Rated Voltage VDC L (Max) 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 10.2

IS61DDPB24M18

Abstract: IS61DDPB22M36
Contextual Info: 72 Mb 2M x 36 & 4M x 18 DDR-IIP (Burst of 2) CIO Synchronous SRAMs . (2.5 Cycle Read Latency) Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

Contextual Info: 72 Mb 2M x 36 & 4M x 18 DDR-IIP (Burst of 2) CIO Synchronous SRAMs . (2.5 Cycle Read Latency) Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

Contextual Info: 72 Mb 2M x 36 & 4M x 18 DDR-IIP (Burst of 2) CIO Synchronous SRAMs . (2.5 Cycle Read Latency) Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

Contextual Info: 72 Mb 2M x 36 & 4M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . Advanced Information January 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

2SD1624

Abstract: u 5601 2SB1124
Contextual Info: Ordering num ber: EN 2019A 2SB1124/2SD1624 NO.2019A SA VYÖ PN P/N PN Epitaxial Planar Silicon Transistors High-Current Switching Applications Applications . Voltage regulators, relay drivers, lamp drivers, electrical equipment. Features . Adoption of FBIT, MBIT processes.

IS61QDB22M36

Abstract: D0-35 IS61QDB24M18
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Two echo clocks (CQ and CQ) that are delivered

Contextual Info: 72 Mb 2M x 36 & 4M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . Advanced Information January 2008 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

IS61DDB22M36-300M3L

Abstract: IS61DDB24M18-300M3L IS61DDB22M36 IS61DDB24M18
Contextual Info: 72 Mb 2M x 36 & 4M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . November 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

IS61DDB22M36

Abstract: IS61DDB24M18
Contextual Info: 72 Mb 2M x 36 & 4M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . Advanced Information February 2008 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

IS61QDB22M18-250M3I

Abstract: D0-35 IDD401 IS61QDB21M36-300M3 IS61QDB21M36-300M3L IS61QDB21M36-250M3LI
Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 2) Synchronous SRAMs . I MAY 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with early write operation.

Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . Advanced Information January 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations.

IS61QDB21M36

Abstract: 61QDB22M18 IS61QDB22M18-250M3I D0-35 IDD401 IS61QDB21M36-300M3 IS61QDB21M36-300M3L IS61QDB21M36-250M3LI MARK D9 IS61QDB22M18-250M3LI
Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 2) Synchronous SRAMs . I JANUARY 2010 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with early write operation.

Contextual Info: 72 Mb 2M x 36 & 4M x 18 7 DDR-II (Burst of 4) CIO Synchronous SRAMs D . I ADVANCED INFORMATION JANUARY 2008 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and write ports. • Synchronous pipeline read with late write operation.