RX2 1017 Search Results

S3320

Contextual Info: DATA SHEET SKY13455-31: 0.4 to 2.7 GHz SP12T Switch with MIPI RFFE Interface Applications • 2G/3G/4G multimode cellular handsets LTE, UMTS, CDMA2000, EDGE, GSM  Embedded data cards TRX1 TRX2 TRX3 Features TRX4 ANT TRX7 TRX8 (RX1) TRX9 (RX2) TRX10 (RX3)

Contextual Info: DATA SHEET SKY18120-11: 0.4-2.7 GHz SP9T Antenna Switch Module With GSM Transmit Filters Applications • Dual-mode, multi-band handsets and data cards GSM/EDGE, Quad/UMTS or LTE dual mode • Low-cost, ultra-small footprint embedded modules Features • Supports quad-band GSM, tri-band UMTS, LTE, or TD-SCDMA

201329F

Contextual Info: DATA SHEET SKY18120-11: 0.4-2.7 GHz SP9T Antenna Switch Module With GSM Transmit Filters Applications • Dual-mode, multi-band handsets and data cards GSM/EDGE, Quad/UMTS or LTE dual mode • Low-cost, ultra-small footprint embedded modules Features • Supports quad-band GSM, tri-band UMTS, LTE, or TD-SCDMA

201576B

Abstract: S2874
Contextual Info: DATA SHEET SKY65364-11: 900 MHz Transmit/Receive Front-End Module Applications Description • Automated meter reading Skyworks SKY65364-11 is a high performance, transmit/receive T/R Front-End Module (FEM). The device provides a complete T/R chain with T/R switches.

SKY65366-11

Abstract: TW21
Contextual Info: DATA SHEET SKY65366-11: 400 MHz Transmit/Receive Front-End Module Applications Description • Automated meter reading Skyworks SKY65366-11 is a high performance, transmit/receive T/R Front-End Module (FEM). The device provides a complete T/R chain with T/R switches.

SKY65313-21

Contextual Info: DATA SHEET SKY65313-21: 900 MHz Transmit/Receive Front-End Module Applications Description • Automated meter reading Skyworks SKY65313-21 is a high performance, transmit/receive T/R Front-End Module (FEM). The device provides a complete T/R chain with T/R switches.

dvi schematic

Abstract: S-PQFP-G100 Package powerPAD layout
Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125 – DECEMBER 2000 D D D D D D D Supports UXGA Resolution Output Pixel Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1 Pin-for-Pin Compatible With TFP501 for Simple Upgrade Path to HDCP2

TFP401

Abstract: 100-PIN TFP401A TFP401APZP TFP401PZP
Contextual Info: TFP401, TFP401A TI PanelBus DIGITAL RECEIVER SLDS120A - MARCH 2000 – REVISED JUNE 2000 D D D D D D D Supports UXGA Resolution Output Pixel Rates Up to 165 MHz Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at

dvi schematic

Abstract: RX-2 -G s S-PQFP-G100 Package powerPAD layout TFP403 TFP501
Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125 – DECEMBER 2000 D D D D D D D Supports UXGA Resolution Output Pixel Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1 Pin-for-Pin Compatible With TFP501 for Simple Upgrade Path to HDCP2

receiver CONTROLLER rx-2

Abstract: dvi schematic diode 101a HSYNC, VSYNC, DE RX-2 -G s S-PQFP-G100 Package powerPAD layout TFP101A tft monitor schematic 100-PIN TFP101
Contextual Info: TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119A - MARCH 2000 – REVISED JUNE 2000 D D D D D D D Supports XGA Resolution Output Pixel Rates Up to 86 MHz Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at 1

100-PIN

Abstract: TFP201 TFP201A TFP201APZP TFP201PZP
Contextual Info: TFP201, TFP201A TI PanelBus DIGITAL RECEIVER SLDS116A - MARCH 2000 – REVISED JUNE 2000 D Supports SXGA Resolution D D D D D D Reduced Power Consumption – 1.8 V Core Output Pixel Rates Up to 112 MHz Digital Visual Interface (DVI) Specification Compliant1

S-PQFP-G100 Package footprint

Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002 D D D D D D D Supports UXGA Resolution Output Pixel Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1 Pin-for-Pin Compatible With TFP501 for

Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A − DECEMBER 2000 − REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1

TFP401

Abstract: 401A TFP401A TFP401APZP TFP401PZP 100-PIN HSYNC, VSYNC, DE, input, output
Contextual Info: TFP401, TFP401A TI PanelBus DIGITAL RECEIVER SLDS120A - MARCH 2000 – REVISED JUNE 2000 D D D D D D D Supports UXGA Resolution Output Pixel Rates Up to 165 MHz Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at

S-PQFP-G100 Package footprint

Abstract: S-PQFP-G100 Package powerPAD layout TFP403 TFP501
Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1

100-PIN

Abstract: TFP101 TFP101A TFP101APZP TFP101PZP HSYNC, VSYNC, DE, input, output
Contextual Info: TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119A - MARCH 2000 – REVISED JUNE 2000 D D D D D D D Supports XGA Resolution Output Pixel Rates Up to 86 MHz Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at 1

Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A − DECEMBER 2000 − REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1

dvi schematic

Abstract: HSYNC, VSYNC, DE receiver CONTROLLER rx-2 RX-2 -G s tmds receiver 100-PIN TFP201 TFP201A TFP201APZP TFP201PZP
Contextual Info: TFP201, TFP201A TI PanelBus DIGITAL RECEIVER SLDS116A - MARCH 2000 – REVISED JUNE 2000 D D D D D D D Supports SXGA Resolution Output Pixel Rates Up to 112 MHz Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at 1

TFP403

Abstract: TFP501
Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1

Hsync Vsync separate

Contextual Info: TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119B - MARCH 2000 – REVISED JANUARY 2003 D D D D D D D Supports XGA Resolution Output Pixel Rates Up to 86 MHz Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at 1

TFP201A

Abstract: TFP201APZP TFP201PZP 100-PIN TFP201 Hsync Vsync decoder HSYNC, VSYNC, DE, input, output
Contextual Info: TFP201, TFP201A TI PanelBus DIGITAL RECEIVER SLDS116A - MARCH 2000 – REVISED JUNE 2000 D D D D D D D Supports SXGA Resolution Output Pixel Rates Up to 112 MHz Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at 1

S-PQFP-G100 Package footprint

Abstract: S-PQFP-G100 Package powerPAD layout RX-2 -G s S-PQFP-G100 Package powerPAD 100-PIN TFP201 TFP201A TFP201APZP TFP201PZP 0.18-um CMOS Flash technology
Contextual Info: TFP201, TFP201A TI PanelBus DIGITAL RECEIVER SLDS116A - MARCH 2000 – REVISED JUNE 2000 D Supports SXGA Resolution D D D D D D Reduced Power Consumption – 1.8 V Core Output Pixel Rates Up to 112 MHz Digital Visual Interface (DVI) Specification Compliant1

Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A − DECEMBER 2000 − REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1

100-PIN

Abstract: TFP101 TFP101A TFP101APZP TFP101PZP
Contextual Info: TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119C - MARCH 2000 − REVISED OCTOBER 2003 D Supports XGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 86 MHz Digital Visual Interface (DVI) Specification Compliant1