RX2 1017 Search Results
RX2 1017 Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
|---|---|---|---|---|---|
| 1017C | Murata Manufacturing Co Ltd | Pulse Transformer, ISOLATION Application(s), 1:1 | |||
| 75844-101-72LF |
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BergStik®, Board to Board connector, Unshrouded vertical header, Through Hole, Double Row, 72 Positions, 2.54mm (0.100in) Pitch. | |||
| 10076801-101-70LF |
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BergStik®, Board to Board connector, Unshrouded Vertical Header, Through Hole, Double row , 70 Positions, 2.54mm (0.100in) Pitch, Pin In Paste | |||
| 10076801-101-72LF |
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BergStik®, Board to Board connector, Unshrouded Vertical Header, Through Hole, Double row , 72 Positions, 2.54mm (0.100in) Pitch, Pin In Paste | |||
| 95278-101-72LF |
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BergStik®, Board to Board connector, Unshrouded vertical header, Surface Mount, Double Row, 72 Positions, 2.54mm (0.100in) Pitch. |
RX2 1017 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
S3320Contextual Info: DATA SHEET SKY13455-31: 0.4 to 2.7 GHz SP12T Switch with MIPI RFFE Interface Applications • 2G/3G/4G multimode cellular handsets LTE, UMTS, CDMA2000, EDGE, GSM Embedded data cards TRX1 TRX2 TRX3 Features TRX4 ANT TRX7 TRX8 (RX1) TRX9 (RX2) TRX10 (RX3) |
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SKY13455-31: SP12T CDMA2000, TRX10 SQ04-0074. 22-pin, J-STD-020) 202952B S3320 | |
201329FContextual Info: DATA SHEET SKY18120-11: 0.4-2.7 GHz SP9T Antenna Switch Module With GSM Transmit Filters Applications • Dual-mode, multi-band handsets and data cards GSM/EDGE, Quad/UMTS or LTE dual mode • Low-cost, ultra-small footprint embedded modules Features • Supports quad-band GSM, tri-band UMTS, LTE, or TD-SCDMA |
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SKY18120-11: 16-pin, J-STD-020) SKY1812yworks 201329F 201329F | |
dvi schematic
Abstract: S-PQFP-G100 Package powerPAD layout
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TFP403 SLDS125 TFP501 dvi schematic S-PQFP-G100 Package powerPAD layout | |
TFP401
Abstract: 100-PIN TFP401A TFP401APZP TFP401PZP
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TFP401, TFP401A SLDS120A TFP401A TFP401 100-PIN TFP401APZP TFP401PZP | |
dvi schematic
Abstract: RX-2 -G s S-PQFP-G100 Package powerPAD layout TFP403 TFP501
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TFP403 SLDS125 TFP501 dvi schematic RX-2 -G s S-PQFP-G100 Package powerPAD layout TFP403 | |
receiver CONTROLLER rx-2
Abstract: dvi schematic diode 101a HSYNC, VSYNC, DE RX-2 -G s S-PQFP-G100 Package powerPAD layout TFP101A tft monitor schematic 100-PIN TFP101
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TFP101, TFP101A SLDS119A TFP101A receiver CONTROLLER rx-2 dvi schematic diode 101a HSYNC, VSYNC, DE RX-2 -G s S-PQFP-G100 Package powerPAD layout tft monitor schematic 100-PIN TFP101 | |
100-PIN
Abstract: TFP201 TFP201A TFP201APZP TFP201PZP
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TFP201, TFP201A SLDS116A TFP201A 100-PIN TFP201 TFP201APZP TFP201PZP | |
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Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A − DECEMBER 2000 − REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1 |
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TFP403 SLDS125A TFP501 | |
TFP401
Abstract: 401A TFP401A TFP401APZP TFP401PZP 100-PIN HSYNC, VSYNC, DE, input, output
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TFP401, TFP401A SLDS120A TFP401A TFP401 401A TFP401APZP TFP401PZP 100-PIN HSYNC, VSYNC, DE, input, output | |
100-PIN
Abstract: TFP101 TFP101A TFP101APZP TFP101PZP CIRCUIT DIAGRAM OF 9 INCH TFT MONITOR
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TFP101, TFP101A SLDS119A TFP101A 100-PIN TFP101 TFP101APZP TFP101PZP CIRCUIT DIAGRAM OF 9 INCH TFT MONITOR | |
100-PIN
Abstract: TFP101 TFP101A TFP101APZP TFP101PZP HSYNC, VSYNC, DE, input, output
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TFP101, TFP101A SLDS119A TFP101A 100-PIN TFP101 TFP101APZP TFP101PZP HSYNC, VSYNC, DE, input, output | |
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Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A − DECEMBER 2000 − REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1 |
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TFP403 SLDS125A TFP501 | |
dvi schematic
Abstract: HSYNC, VSYNC, DE receiver CONTROLLER rx-2 RX-2 -G s tmds receiver 100-PIN TFP201 TFP201A TFP201APZP TFP201PZP
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TFP201, TFP201A SLDS116A TFP201A dvi schematic HSYNC, VSYNC, DE receiver CONTROLLER rx-2 RX-2 -G s tmds receiver 100-PIN TFP201 TFP201APZP TFP201PZP | |
TFP403
Abstract: TFP501
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TFP403 SLDS125A TFP501 TFP403 | |
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TFP201A
Abstract: TFP201APZP TFP201PZP 100-PIN TFP201 Hsync Vsync decoder HSYNC, VSYNC, DE, input, output
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TFP201, TFP201A SLDS116A TFP201A TFP201APZP TFP201PZP 100-PIN TFP201 Hsync Vsync decoder HSYNC, VSYNC, DE, input, output | |
circuit diagram of stag 300Contextual Info: TFP401, TFP401A TI PanelBus DIGITAL RECEIVER SLDS120B - MARCH 2000 – REVISED JUNE 2003 D D D D D D D Supports UXGA Resolution Output Pixel Rates Up to 165 MHz Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at |
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TFP401, TFP401A SLDS120B circuit diagram of stag 300 | |
0.18-um CMOS technology zigbee
Abstract: TFP403 TFP501 HSYNC, VSYNC, DE
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TFP403 SLDS125A TFP501 0.18-um CMOS technology zigbee TFP403 HSYNC, VSYNC, DE | |
S-PQFP-G100 Package powerPAD layoutContextual Info: TFP201, TFP201A TI PanelBus DIGITAL RECEIVER SLDS116A - MARCH 2000 – REVISED JUNE 2000 D Supports SXGA Resolution D D D D D D Reduced Power Consumption – 1.8 V Core Output Pixel Rates Up to 112 MHz Digital Visual Interface (DVI) Specification Compliant1 |
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TFP201, TFP201A SLDS116A S-PQFP-G100 Package powerPAD layout | |
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Contextual Info: TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119C - MARCH 2000 − REVISED OCTOBER 2003 D Supports XGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 86 MHz Digital Visual Interface (DVI) Specification Compliant1 |
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TFP101, TFP101A SLDS119C | |
Theta-JCContextual Info: TFP401, TFP401A TI PanelBus DIGITAL RECEIVER SLDS120B - MARCH 2000 − REVISED JUNE 2003 D Supports UXGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 165 MHz Digital Visual Interface (DVI) Specification Compliant1 |
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TFP401, TFP401A SLDS120B Theta-JC | |
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Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125B − DECEMBER 2000 − REVISED MAY 2011 D 4x Over-Sampling for Reduced Bit-Error D Supports Pixel Rates Up to 165MHz D D D D D Including 1080p and WUXGA at 60 Hz Digital Visual Interface (DVI 1.0) Specification Compliant1 |
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TFP403 SLDS125B 165MHz 1080p TFP501 | |
S-PQFP-G100 Package footprint
Abstract: S-PQFP-G100 Package powerPAD layout
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TFP403 SLDS125A TFP501 S-PQFP-G100 Package footprint S-PQFP-G100 Package powerPAD layout | |
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Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125B − DECEMBER 2000 − REVISED MAY 2011 D Supports Pixel Rates Up to 165MHz D D D D D D 4x Over-Sampling for Reduced Bit-Error Including 1080p and WUXGA at 60 Hz Digital Visual Interface (DVI 1.0) Specification Compliant1 |
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TFP403 SLDS125B 165MHz 1080p TFP501 | |
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Contextual Info: TFP201, TFP201A TI PanelBus DIGITAL RECEIVER SLDS116A - MARCH 2000 − REVISED JUNE 2000 D Supports SXGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 112 MHz Digital Visual Interface (DVI) Specification Compliant1 |
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TFP201, TFP201A SLDS116A | |