RX-3E 8 Search Results

mb3775 inverter

Abstract: f16015
Contextual Info: FUJITSU SEM ICONDUCTOR DATA SHEET DS04-27204-3E • ■c. . ■■■ ill Ì.S IB V rX ?. m m I m ■» * J I B m LOW VOLTAGE DUAL PWM SWITCHING REGULATOR CONTROLLER The MB3775 is a dual pulse-width-modulation control circuit. It contains the basic circuits required for two PWM control circuits. Complete synchronization is

RX 3E

Abstract: CRC-10 MXT3010 Maker Communications RX- 3E
Contextual Info: Maker MXT3010 Cell Length Application Note Application Note #8 Revision 1.0 2/11/97 Maker Communications, Inc. 486 Totten Pond Road • Waltham, Massachusetts 02154 617.672.0622 • Fax 617.672.0256 February 1997 Copyright 1997 by Maker Communications, Inc. All rights reserved. Printed in the United States of America.

TCA 810

Abstract: RX 3E GR-253-CORE PM5355 SUNI-622
Contextual Info: PM5355 S/UNI-622 Errata PMC-950217 ISSUE 7 SUNI-622 DATASHEET ERRATA PM5355 S/UNI-622 DATASHEET ERRATA Issue 7: March, 1998 PMC-Sierra, Inc 105-8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415 PM5355 S/UNI-622 Errata PMC-950217 ISSUE 7 SUNI-622 DATASHEET ERRATA

GR253-CORE

Abstract: PM5347
Contextual Info: PM5347 S/UNI-PLUS ERRATA PMC-951110 ISSUE 9 S/UNI-PLUS DATASHEET ERRATA PM5347 SATURN USER NETWORK INTERFACE PLUS ERRATA ISSUE 9: JUNE 1998 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers Internal Use. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

Contextual Info: 8 6 7 3 5 2 C\J E D RECOMMENDED PCB PATTERN LAYOUT 5C A LE :2- I if f 0E( , NO LU < — O a) N 0TES 1. m MATERIAL 00 PPSx&Ss ( t = 0.2 ) VACUUM C0 V ER ;5T A IN LES5 STEEL 2. X y lf tS k PLATING CONTACT AREA:G0LD 0 .2 5 p m M I N . ¥ f fltti:m p : m > < ^ + PS n /P b = 9 0 /l0 (X )

la 5531

Abstract: s0245 jb 5531 JT MARKING T108 T46C sf 340 7 flu 0286
Contextual Info: NEC 7 s— S * h* M -ê - h i ï 7 . 9 > Compound Transistor m ^ T /ÿ rx FAI L4L S £ ttP *3 M N P N x t :9 ^ > T J U m > lJ □ > h ^ > i> X ? 4 » iE 4# m t '• mm $ o ;< 4 1* 1/1 L R i = 4 7 kQ, t > ' i 1 "0 R 2 = 22 k Q ) 2 . 8 + 0.2 o.65±8:is 1 .5

Contextual Info: Pin Information for the Stratix V 5SGSD6 Device Version 1.1 Note 1 Bank Number GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2

Contextual Info: Pin Information for the Stratix V 5SGSD8 Device Version 1.1 Note 1 Bank Number GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2

Contextual Info: Pin Information for the Stratix V 5SEE9 Device Version 1.1 Note 1 Bank Number 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B

Contextual Info: Pin Information for the Stratix V 5SGXAB Device Version 1.1 Note 1 Bank Number GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2

Contextual Info: Pin Information for the Stratix V 5SEEB Device Version 1.1 Note 1 Bank Number 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B

Contextual Info: Pin Information for the Stratix V 5SGXA9 Device Version 1.1 Note 1 Bank Number GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2 GXB_L2

TMS 3529

Abstract: Texas Instruments MSP430G2xx GANG430 splitter schematic SLAU358B GANG430U MSP430F261 MSP430Fe4xx MSP430FR5738 jtag programmer guide
Contextual Info: MSP Gang Programmer MSP-GANG User's Guide Literature Number: SLAU358B September 2011 – Revised June 2012 Contents . 6

Contextual Info: MSP Gang Programmer MSP-GANG User's Guide Literature Number: SLAU358F September 2011 – Revised July 2014 Contents Preface . 6

DSC 5D

Abstract: SOH DX1 ed 49 E5 0D imf29 C4029B 47029B MHNA2W.00 A41E AN-345
Contextual Info: UniSLIC14 and the IDT821068 Programmable Octal CODEC Application Note AN-345 Author: Don LaFontaine Intersil ,Q WUR URG GX FWL FWLR RQ The purpose of this application note is to provide a reference design for the UniSLIC14 and IDT821068 Programmable Octal CODEC.

AN9948

Abstract: ecf 83 IDT821068 9948 HC55185 A41E
Contextual Info: UniSLIC14 and the IDT821068 Programmable Octal CODEC TM Application Note December 2001 AN9948 Author: Don LaFontaine Reference Design using the UniSLIC14 and the IDT821068 Programmable Octal CODEC ZO, Figure 1 equal to the desired terminating impedance ZL,

l4141

Contextual Info: S71NS128JA0/S71NS064JA0 Stacked Multi-Chip Product MCP 128 Megabit (8 M x 16-Bit) and 64 Megabit (4 M x 16-Bit), 110 nm CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memories with 16 Megabit (1M x 16-Bit) pSRAM Data Sheet ADVANCE INFORMATION

LT 2807

Contextual Info: Z £ - rX M Z £ 0 D I 0-N3 's h STICK 6 7 8 )ì) NOTES. 1. 9 10 12 BOTH ENDS WITH CAPS. 600 ±2 TOTAL LENGTH THICKNESS 'IB s SD -5 27 6 0 -*0 ^ #^ T SL'o 4. S EE SD-52760-*0 FOR AVAIR ABLE ITEMS. < ce O R D - 1209 - 1009 -0909 -0809 -0709 -0689 -0609

DS31400

Abstract: OTU2 framer automatic phase selector circuit diagram AUTOMATIC PHASE SELECTOR for three phase AUTOMATIC PHASE SELECTOR ocxo 25MHz 3 phase automatic phase selector NX-19
Contextual Info: ABRIDGED DATA SHEET 19-5256; Rev 1; 11/10 DS31400 8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter General Description The DS31400 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its eight input clocks

MC68824

Abstract: duobinary encoder M68000 MC68184 SMIND
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC68184 Technical Sum m ary Broadband Interface Controller The MC68184 broadband interface controller BIC is a high-performance inter­ face device for use with the MC68824 token bus controller (TBC) to implement the digital portion of the physical layer of a broadband IEEE 802.4 token bus

Contextual Info: Pin Information for the Stratix V 5SGXA5 Device Version 1.2 Note 1 Bank Number GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1

Contextual Info: Pin Information for the Stratix V 5SGXA7 Device Version 1.2 Note 1 Bank Number GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1

AUTOMATIC PHASE SELECTOR for three phase

Abstract: OTU1
Contextual Info: Short Form Data Sheet April 2012 DS31400 8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter General Description The DS31400 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its eight input clocks

C5393

Abstract: l273
Contextual Info: t InNET TECHNOLOGIES T0140S Electrical REV. 01 E L E C T R IC A L S P E C IF IC A T IO N S TURNS RATIO: (TXIN+)—(CTIN)—(TXIN—) : ( 7 X 0 + ) - ( C T 0 ) - ( T X 0 - ) 1CT : 1CT ± 3% (R X O + )—(RXO—) : (R X IN + )—(RXIN—) 1 : 1 ± 3% l •1