RQ 300 W Search Results

20A60

Abstract: RQ 300 W
Contextual Info: MOTOROLA Order this document by MHPM6B1OA6OD/D SEMICONDUCTOR TECHNICAL DATA Preliminary Data Sheet M HPM 6B10A60D M H PM 6B20A60D H y b rid P o w e r M o d u le Motorola Preferred Devices Integrated Power Stage for 230 VAC Motor Drives 10, 20 AMP, 600 V HYBRID POWER MODULES

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SK10GHR123

Abstract: SK10GHR123I
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Abstract: semikron sk 60 gl
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skm 195 gb 125 dn

Abstract: B124D xvh20
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1371r

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Contextual Info: IE Cermet rotary potentiometers Series 4 5 6 O rdering code no.: 21 456 0. Type HC 4 5 6 /3 0 Basic design: encased knob, double metai wiper, drive position ,S" Special versions - Snap-in terminals - Carbon contact wiper - Cover with scale Technical data

QDR pcb layout

Abstract: A7236 M5M5V5636GP M5M5V5A36GP 165-BGA 165BGA
Contextual Info: Renesas Memories General Presentation October 2010 Renesas Fast SRAM Renesas Electronics Corporation System Solution Business Unit4 System Solution Business Group 10/01/2010 2-1 Rev.2.00 2010. Renesas Electronics Corporation. All rights reserved.

diode code GW 17

Abstract: EA-088-0204 GK SOT23 MARK LDR655312T-100 L10uH
Contextual Info: 5;B GRF STEP-UP DC/DC CONTROLLER NO. EA-088-0204 5[ 6(5,(6 OUTLINE 7KH 5[ 6HULHV DUH &026EDVHG 3:0 VWHSXS '&'& FRQYHUWHU FRQWUROOHUV ZLWK ORZ VXSSO\ FXUUHQW (DFK RI WKH 5[ 6HULHV FRQVLVWV RI DQ RVFLOODWRU D 3:0 FRQWURO FLUFXLW D UHIHUHQFH YROWDJH XQLW DQ HUURU DPSOL

60GB123

Abstract: a3113
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rake complex

Abstract: SC140 Scrambling code "DS-CDMA" "channel estimation"
Contextual Info: Application Note AN2251/D Rev 1, 2/2002 Maximum Ratio Combining for a WCDMA Rake Receiver by Kim-Chyan Gan CONTENTS 1 System Model. 1 2 Chip/Symbol Rate Combining . 2 3 Implementation in StarCore . 5

m35sp mitsumi

Abstract: m35sp-8 mitsumi stepping motor m35sp 8 m35sp 8 495p
Contextual Info: MITSUMI Stepping Motors M35SP-8 Stepping Motors OUTLINE "M35SP-8" has been endowed with the highest output torque among the 35mm outer diameter model series-holding torque : 38.2mN•m, pullout torque : 23.0mN·m/200pps, and pull-in torque : 22.5mN·m/200pps 12V DC .

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Contextual Info: Preliminary GS82582QT19/37E-400/375/333/300 288Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

2sc4977

Abstract: transistor 2SC4977 25c2625 2SC2625 2SC2047 2SC4977 transistor ET-191 2SC4795 2SC3320 ET391
Contextual Info: FUJI <S SWITCHING TRANSISTORS B| TO-220AB T O -3 P • t ' 5 /% ■m * 1 * 1 T O -3 P F BBS 1C AMPS Max. 3 80 Device Type NPN 2SC3550 180 80 2SD921 800 80 2SC3551 1000* 80 ET383 V ceoV sus 800 5 Pc W IC AMPS Max. 400 60 Device Type NPN 2SC2929 800 40 2SC3549

Contextual Info: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions

ms0369

Abstract: MPX16 AK7746VT
Contextual Info: [ASAHI KASEI] [AK7746] AK7746 Audio DSP with 5-channel 24-bit ADC and Input Mux 1. General Description The AK7746 is a highly integrated audio processor, including 5 A/D channels, an input mux that can select 2 stereo pairs from 8 stereo inputs, and an on-chip DSP. High quality analog performance is provided by the ADC’s achieving 98dB

Contextual Info: CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports

Hitachi DSA00276

Contextual Info: HM62G18512A Series 8M Synchronous Fast Static RAM 512k-word x 18-bit ADE-203-1268A (Z) Preliminary Rev. 0.1 Jun. 6, 2001 Description The HM62G18512A is a synchronous fast static RAM organized as 512-kword × 18-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing