RLDRAM 3 Search Results

RLDRAM

Abstract: content addressable memory low power ternary "Content Addressable Memory" ternary
Contextual Info: RLDRAM 2 Memory: Addressing Networking Memory Requirements ISSI’s RLDRAM 2 Memory is a reduced-latency DRAM that offers fast random access 20ns tRC , making RLDRAM ideal for communication applications ranging from access nodes to core routers. table applications. Additionally, RLDRAM’s large density

Contextual Info: 256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM Features Reduced Latency DRAM RLDRAM MT49H8M32 – 1 Meg x 32 x 8 banks MT49H16M16 – 2 Meg x 16 x 8 banks For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/dram/rldram/

RLDRAM

Contextual Info: RLDRAM II Controller MegaCore Function Errata Sheet March 2007, MegaCore Version 7.0 This document addresses known errata and documentation issues for the RLDRAM II Controller MegaCore function version 7.0. Errata are functional defects or errors, which may cause the RLDRAM II Controller

transistor SMD DKL

Abstract: BA5 marking MARKING SMD x9 Micron DDR marking H12 smd cod A22 SMD MARKING CODE A53 SMD Marking Code marking BAX marking code a02 SMD Transistor Marking D1c
Contextual Info: 288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Features 288Mb CIO Reduced Latency RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 For the latest data sheet, refer to Micron’s Web site: www.micron.com/rldram Features Figure 1: • 400 MHz DDR operation (800 Mb/s/pin data rate)

RLDRAM

Abstract: diode V6
Contextual Info: RLDRAM II Controller MegaCore Function Errata Sheet December 2006, MegaCore Version 6.1 This document addresses known errata and documentation issues for the RLDRAM II Controller MegaCore function version 6.1. Errata are functional defects or errors, which may cause the RLDRAM II Controller

MT49H16M18C

Contextual Info: 16 Meg x 18 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II Features 288Mb SIO Reduced Latency RLDRAM II MT49H16M18C For the latest data sheet, refer to Micron’s Web site: www.micron.com/rldram Features Figure 1: • 400 MHz DDR operation (800 Mb/s/pin data rate)

15READ

Abstract: marking ba5 MT49H8M18C MT49H16M18C
Contextual Info: 288Mb: 16 Meg x 18 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II Features 288Mb SIO Reduced Latency RLDRAM II MT49H16M18C For the latest data sheet, refer to Micron’s Web site: www.micron.com/rldram Features Figure 1: • 400 MHz DDR operation (800 Mb/s/pin data rate)

hspice MT49H16M36

Abstract: MT49H16M36FM MT49H16M36 MT49H32M18FM
Contextual Info: Advance‡ 576Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Features 576Mb CIO Reduced Latency RLDRAM II MT49H16M36 MT49H32M18 MT49H64M9 For the latest data sheet, refer to Micron’s Web site: www.micron.com/rldram Features Figure 1: • 533 MHz DDR operation (1,067 Mb/s/pin data rate)

09005aef809f284b

Contextual Info: 288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Features 288Mb CIO Reduced Latency RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 Features Figure 1: • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization 8 Meg x 36, 16 Meg x 18, and 32 Meg x 9

MT49H16M18

Contextual Info: ADVANCE‡ 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288Mb CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 FEATURES Figure 1 144-Ball µBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

Contextual Info: RLDRAM II Controller MegaCore Function Release Notes May 2007, MegaCore Version 7.1 These release notes for the RLDRAM II Controller MegaCore function version 7.1 contain the following information: • ■ ■ ■ ■ System Requirements System Requirements

BA6A

Abstract: marking code d2c smd
Contextual Info: 256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM REDUCED LATENCY DRAM RLDRAM MT49H8M32 – 1 Meg x 32 x 8 Banks MT49H16M16 – 2 Meg x 16 x 8 Banks Features Figure 1: 144-Ball µFBGA • 256Mb • Organization 8 Meg x 32, 16 Meg x 16 in 8 banks

Contextual Info: RLDRAM II Controller MegaCore Function Release Notes March 2007, MegaCore Version 7.0 These release notes for the RLDRAM II Controller MegaCore function version 7.0 contain the following information: • ■ ■ ■ ■ System Requirements System Requirements

RLDRAM

Abstract: AMD64
Contextual Info: RLDRAM II Controller MegaCore Function October 2005, MegaCore Version 1.0.0 Release Notes These release notes for the RLDRAM II Controller MegaCore function version 1.0.0 contain the following information: • ■ ■ ■ ■ System Requirements System Requirements

AMD64

Abstract: RLDRAM
Contextual Info: RLDRAM II Controller MegaCore Function Release Notes April 2006, MegaCore Version 1.1.0 These release notes for the RLDRAM II Controller MegaCore function version 1.1.0 contain the following information: • ■ ■ ■ ■ ■ System Requirements System Requirements

MT49H16M18

Contextual Info: ADVANCE‡ 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288Mb CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 FEATURES Figure 1 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

RLDRAM

Abstract: MT49H16M18C
Contextual Info: 288Mb: x18 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM 2 Features SIO RLDRAM 2 MT49H16M18C – 16 Meg x 18 x 8 banks Features Options1 • 533 MHz DDR operation 1.067 Gb/s/pin data rate • 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) • Organization

MT49H16M18

Contextual Info: 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288MB CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

576mb

Abstract: MT44K16M36PA-093E
Contextual Info: 576Mb: x18, x36 RLDRAM 3 Features RLDRAM 3 MT44K32M18 – 2 Meg x 18 x 16 Banks MT44K16M36 – 1 Meg x 36 x 16 Banks Options1 Features • Clock cycle and tRC timing – 0.93ns and tRC MIN = 8ns (RL3-2133) – 0.93ns and tRC (MIN) = 10ns (RL3-2133) – 1.07ns and tRC (MIN) = 8ns

MT49H16M18C

Contextual Info: ADVANCE‡ 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY RLDRAM II MT49H16M18C MT49H32M9C FEATURES Figure 1 144-Ball µBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization - 16 Meg x 18, 32 Meg x 9 Separate I/O

MICRON BGA PART MARKING

Abstract: RLDRAM 09005aef809f284b MT49H16M36
Contextual Info: 576Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II Features CIO RLDRAM II MT49H64M9 – 64 Meg x 9 x 8 Banks MT49H32M18 – 32 Meg x 18 x 8 Banks MT49H16M36 – 16 Meg x 36 x 8 Banks Features Figure 1: • 533 MHz DDR operation 1.067 Gb/s/pin data rate

MT49H16M36

Abstract: MT49H32M18C
Contextual Info: 576Mb: x9, x18 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II Features SIO RLDRAM II MT49H32M18C – 32 Meg x 18 x 8 banks MT49H64M9C – 64 Meg x 9 x 8 banks Features Figure 1: • 533 MHz DDR operation 1.067 Gb/s/pin data rate • 38.4 Gb/s peak bandwidth (x18 at 533 MHz clock

MT49H16M36

Contextual Info: 576Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II Features CIO RLDRAM II MT49H64M9 – 64 Meg x 9 x 8 Banks MT49H32M18 – 32 Meg x 18 x 8 Banks MT49H16M36 – 16 Meg x 36 x 8 Banks Features Figure 1: • 533 MHz DDR operation 1.067 Gb/s/pin data rate

MT49H16M18

Contextual Info: 288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II Features CIO RLDRAM II MT49H32M9 – 32 Meg x 9 x 8 Banks MT49H16M18 – 16 Meg x 18 x 8 Banks MT49H8M36 – 8 Meg x 36 x 8 Banks Features Figure 1: • 400 MHz DDR operation 800 Mb/s/pin data rate