RL-9720 0 Search Results

RL-9720 0

Abstract: RL-9720
Contextual Info: RL-9720 LOW PROFILE SMD POWER INDUCTOR DESCRIPTION FEATURES & APPLICATIONS • SMD Power Inductor • • • ENVIRONMENTAL DATA • • Storage temperature range: -55°C to +130°C Operating temperature range: -40°C to +130°C Low profile surface mount inductors in a small package size

Contextual Info: RL-9720 SHIELDED SMD POWER INDUCTOR DESCRIPTION FEATURES & APPLICATIONS • SMD Power Inductor • • • ENVIRONMENTAL DATA • • Storage temperature range: -55°C to +130°C Operating temperature range: -40°C to +130°C Low profile surface mount inductors in a small package size

813N252BKI-09LFT

Contextual Info: VCXO Jitter Attenuator & FemtoClock Multiplier ICS813N252I-09 DATA SHEET General Description Features The ICS813N252I-09 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency

813N252AKI-09LFT

Abstract: 3155MW HC49 ICS813N252AKI-09 ICS813N252I-09 MO-220 813N252AKI-09LF
Contextual Info: VCXO Jitter Attenuator & FemtoClock Multiplier ICS813N252I-09 DATA SHEET General Description Features The ICS813N252I-09 is a PLL based synchronous multiplier that is optimized for PDH or SONET to HiPerClockS™ Ethernet clock jitter attenuation and frequency

transistor 9720

Abstract: smd 19.44 MHz lvttl HC49 ICS813322-02 ICS813322BK-02 MO-220 loop heat pipes 813322 ics813322
Contextual Info: PRELIMINARY ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER GENERAL DESCRIPTION FEATURES • Two differential LVPECL outputs Each output supports independent frequency selection at 19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz The ICS813322-02 is a member of the

transistor SMD qb

Contextual Info: VCXO Jitter Attenuator & FemtoClock NG Multiplier ICS813N252I-04 DATA SHEET General Description Features The ICS813N252I-04 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency

MO-220

Abstract: HC49 ICS13252I-02 ICS813252CKI-02 ICS813252I-02 ICS3252CI02 32-VFQFN
Contextual Info: Jitter Attenuator & FemtoClock Multiplier ICS813252I-02 DATA SHEET GENERAL DESCRIPTION FEATURES The ICS813252I-02 is a PLL based synchronous ICS multiplier that is optimized for PDH or SONET to HiPerClockS™ Ethernet clock jitter attenuation and frequency

AD9950

Contextual Info: ANALOG DEVICES FEATURES 400 MSPS ECU/100 MSPS (TTL Update Rate Low Glitch Impulse: 1.5 pV-s Fast Settling: 4.5 ns to 1/2 LSB Low Power: 1.1 W On-Board Quadrature Logic for DDS Applications Differential Clock (ECL) APPLICATIONS Direct Digital Synthesis Arbitrary Waveform Synthesis

97A8

Abstract: cable tv amplifier MAX496 MAX496CPE MAX496CSE MAX497
Contextual Info: 19-0373; Rev 1; 12/98 L MANUA ION KIT HEET T A U L EVA TA S WS DA FOLLO 375MHz Quad Closed-Loop Video Buffers, AV = +1 and +2 _Features The MAX496 and MAX497 are quad, closed-loop, ±5V video buffers that feature extremely high bandwidth and

MAX3831

Abstract: MAX3831UCB MAX3832 MAX3832UCB MAX3876
Contextual Info: 19-1534; Rev 0; 8/99 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator Features ♦ +3.3V Single Supply ♦ 1.6W Power Dissipation ♦ 4-Channel Mux/Demux with Fully Integrated 2.488GHz Clock Generator ♦ Frame Detection Maintains Channel Assignment

MAX3831

Abstract: MAX3831UCB MAX3832 MAX3832UCB MAX3876
Contextual Info: 19-1534; Rev 1; 10/99 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator Features ♦ +3.3V Single Supply ♦ 1.45W Power Dissipation MAX3831 ♦ 4-Channel Mux/Demux with Fully Integrated 2.488GHz Clock Generator ♦ Frame Detection Maintains Channel Assignment

pecl logic voltage levels

Contextual Info: 19-1534; Rev 1; 10/99 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator Features ♦ +3.3V Single Supply ♦ 1.45W Power Dissipation MAX3831 ♦ 4-Channel Mux/Demux with Fully Integrated 2.488GHz Clock Generator ♦ Frame Detection Maintains Channel Assignment

Contextual Info: TPS68000 6,4 mm x 7,8 mm www.ti.com SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006 HIGHLY EFFICIENT PHASE SHIFT FULL BRIDGE CCFL CONTROLLER FEATURES • • • • • • • • • • • • DESCRIPTION 8-V to 30-V Input Voltage Range Full Bridge Topology With Integrated Gate

Contextual Info: TLC5944 TL C5 94 4 TL C5 944 www.ti.com . SBVS112A – JUNE 2008 – REVISED JULY 2009 16-Channel, 12-Bit PWM LED Driver with

Contextual Info: TLC5944 TL C5 94 4 TL C5 944 www.ti.com . SBVS112 – JUNE 2008

Contextual Info: TLC5944 TL C5 94 4 TL C5 944 www.ti.com . SBVS112A – JUNE 2008 – REVISED JULY 2009 16-Channel, 12-Bit PWM LED Driver with

Contextual Info: TLC5944 TL C5 94 4 TL C5 944 www.ti.com . SBVS112A – JUNE 2008 – REVISED JULY 2009 16-Channel, 12-Bit PWM LED Driver with

Contextual Info: TPS68000 6,4 mm x 7,8 mm www.ti.com SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006 HIGHLY EFFICIENT PHASE SHIFT FULL BRIDGE CCFL CONTROLLER FEATURES • • • • • • • • • • • • DESCRIPTION 8-V to 30-V Input Voltage Range Full Bridge Topology With Integrated Gate

Contextual Info: Not Recommended for New Designs TPS68000 6,4 mm x 7,8 mm www.ti.com SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006 HIGHLY EFFICIENT PHASE SHIFT FULL BRIDGE CCFL CONTROLLER Check for Samples: TPS68000 FEATURES 1 • • 2 • • • • • • •

POL 4558

Abstract: tda 4558 tda 7830 tda 8555 1mo 565 tda 3377 amd 5400 architecture and features TDA 4422 crc circuits polynomials intel 433 mhz rr10
Contextual Info: WON 2 i 1991 Cl Advanced Micro Devices Am8030/Am8530 H Serial Communications Controller DISTINCTIVE CHARACTERISTICS • ■ ■ ■ Two 0 to 2 Mb/s full duplex serial channels Programmable synchronous modes — Each channel has independent oscillator, baud-rate generator, and PLL for clock

6n60

Abstract: CDCE18005 CDCE62005 QFN-48 S-PQFP-N48 QFN-48 6x6
Contextual Info: CDCE18005 www.ti.com. SCAS863 – NOVEMBER 2008 Five/Ten Output Clock Generator/Buffer

CDCE62005

Abstract: S-PQFP-N48 CDCE18005 QFN-48 LE 9540
Contextual Info: CDCE18005 www.ti.com. SCAS863 – NOVEMBER 2008 Five/Ten Output Clock Generator/Buffer

34AH

Abstract: MCP101-270/IC HS 8110
Contextual Info: :2 0: 07 PM Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Released m be r, 20 07 10 PM4318 nd ay ,1 6S ep te OCTLIU Data Sheet Proprietary and Confidential Released Issue No. 6: May 2002 Do wn l oa de d by I HS Pa r ts Ma na g em

FM TRANSMITTER CIRCUIT DIAGRAM

Abstract: atm header-error-check multiple bit cell broadband single LOAD CELL ML53301 UTOPIA-11 laf 0001 for power supply of LCD monitor diagram
Contextual Info: V f M L53301-98-08- 12.fm Page 1 Thursday, August 27, 1998 9:31 PM Table of Contents 1. D escription. 5