REGISTER AND CONTROL Search Results

Contextual Info: L29C818 Serial Scan Register Features Description □ Octal register with additional 8-bit shiftable shadow register The L29C818 is a high-speed octal register designed especially for appli­ cations using serial-scan diagnostics or writable control store. It is pin and

mq7 gas

Abstract: am2914 5607
Contextual Info: Am 2914 Vectored Priority Interrupt Controller > 3 DISTINCTIVE CHARACTERISTICS FO to Accepts 8 interrupt inputs Interrupts may be pulses or levels and are stored internally Built-in mask register Six different operations can be performed on mask register Built-in status register Status register holds code for lowest allowed in­

Contextual Info: CHAPTER 3 FUNCTIONS This chapter describes the functions of SPC internal registers, memory, and buffers. 3.1 INTERNAL REGISTERS 3.2 BASIC CONTROL REGISTER 3.3 INITIAL SETTING REGISTER WINDOW 3.4 MCS BUFFER WINDOW 3.5 USER PROGRAM MEMORY WINDOW 3.6 SCAM REGISTER WINDOW

74LVC594A

Abstract: 74LVC594ABQ 74LVC594AD 74LVC594APW DHVQFN16 TSSOP16
Contextual Info: 74LVC594A 8-bit shift register with output register Rev. 01 — 24 May 2007 Product data sheet 1. General description The 74LVC594A is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on both shift and storage registers.

TC4094B

Abstract: TC4094BF TC4094BFN TC4094BP
Contextual Info: TC4094BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4094BP,TC4094BF,TC4094BFN TC4094B 8-Stage Shift-and-Store Bus-Register TC4094B is a SHIFT and STORE REGISTER that consists of an 8-bit shift register and an 8-bit latch. The read data in the

54ACT818

Abstract: 54ACT 74S818
Contextual Info: 54ACT818 8-Bit Diagnostic Register General Description The ’ACT818 is a high-speed, general-purpose pipeline register with an on-board diagnostic register for performing serial diagnostics and/or writable control store loading. The D-to-Y path provides an 8-bit parallel data path pipeline

DM74AS651

Abstract: DM74AS651NT DM74AS651WM DM74AS652 DM74AS652NT DM74AS652WM M24B MS-013 N24C
Contextual Info: Revised March 2000 DM74AS651 • DM74AS652 Octal Bus Transceiver and Register General Description Features These devices incorporate an octal transceiver and an octal D-type register configured to enable transmission of data from bus to bus or internal register to bus. The

DM74ALS646

Abstract: DM74ALS646NT DM74ALS646WM M24B MS-013 N24C
Contextual Info: Revised February 2000 DM74ALS646 Octal 3-STATE Bus Transceiver and Register General Description Features This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to

815C

Abstract: DM74AS646 DM74AS646NT DM74AS646WM DM74AS648 DM74AS648NT DM74AS648WM M24B MS-013 N24C
Contextual Info: Revised March 2000 DM74AS646 • DM74AS648 Octal Bus Transceiver and Register General Description Features This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to

74LVC595A

Abstract: 74LVC595ABQ 74LVC595AD 74LVC595APW DHVQFN16 TSSOP16
Contextual Info: 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 01 — 29 May 2007 Product data sheet 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks.

Contextual Info: 19-2698; Rev 3; 2/05 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset Features The MAX7310 provides 8-bit parallel input/output port expansion for SMBus -compatible and I2C-compatible applications. The MAX7310 consists of an input port register, an output port register, a polarity inversion register, a configuration register, a bus timeout register,

SMM150

Abstract: Summit Microelectronics zx1001
Contextual Info: Application Note 46 SMM150 Single-Channel Supply Voltage Marginer, Monitor and DC Output Controller Windows GUI Users Guide and Configuration Register Descriptions Introduction The information contained in Application Note 46 details the Configuration Register settings for the

SMM766

Contextual Info: Application Note 51 SMM766 Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer Windows GUI Users Guide and Configuration Register Descriptions Introduction The information contained in Application Note 51 details the Configuration Register settings for the

MC14517

Abstract: MC14517B MC14517BCP MC14517BDW MC14517BDWR2 14517b Q32B
Contextual Info: MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data

MC14517

Abstract: 14517B Q32B Q32A
Contextual Info: MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64−bit static shift register consists of two identical, independent, 64−bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data

DM74AS646

Abstract: DM74AS646NT DM74AS646WM DM74AS648NT DM74AS648WM M24B N24C
Contextual Info: 646 • 648 National Semiconductor DM74AS646/DM74AS648 Octal Bus Transceiver and Register General Description This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed trans­ mission of data from bus to bus or internal register to bus.

74ALS652-1NT

Abstract: 74ALS652-1WM DM74ALS652 DM74ALS652NT DM74ALS652WM M24B N24C
Contextual Info: 652 • 652-1 National Semiconductor DM74ALS652/74ALS652-1 Octal TRI-STATE Bus Transceiver and Register General Description This device incorporates an octal transceiver and an octal D-type register configured to enable transmission of data from bus to bus or internal register to bus.

S80C196NU

Abstract: a2823 80C196NU 8XC196NP 8XC196NU AD10 a2824 SB80C196NU 16 bit MCS-96 microcontroller
Contextual Info: PRELIMINARY 8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER • 50 MHz Operation† ■ 1 Mbyte of Linear Address Space ■ Optional 48 Kbytes of ROM ■ 1 Kbyte of Register RAM ■ Register-register Architecture ■ Footprint and Functionally Compatible

Contextual Info: 74LS295B Signetics Shift Register 4-Bit Shift Register With 3-State Outputs Product Specification Logic Products FEATURES • 4-bit parallel load shift register • Independent 3-State buffer outputs • See '395 for serial expansion and Master Reset version

HD74AC194

Abstract: Hitachi DSA003764
Contextual Info: HD74AC194 4-bit Bidirectional Unviersal Shift Register Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs,

Contextual Info: E M IC O N D U C T Q R t DM74AS646/DM74AS648 Octal Bus Transceiver and Register General Description This device incorporates an octal bus transceiver and an oc­ tal D-type register configured to enable multiplexed trans­ mission of data from bus to bus or internal register to bus.

LVCH646A

Abstract: SO24-2
Contextual Info: IDT74LVCH646A 3.3V CMOS OCTAL BUS TRANSCEIVER AND REGISTER EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVCH646A ADVANCE INFORMATION 3.3V CMOS OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: – – – – – – – – –

27S85

Contextual Info: a Am27S85 16,384-Bit 4096 x 4 Registered PROM with SSR Diagnostics Capability > 3 DISTINCTIVE CHARACTERISTICS On-chip diagnostic shift register for serial observability and controllability of the output register User-programmable for Asynchronous Enable, Synchro­

ML5805

Abstract: AN-096
Contextual Info: AN RFMD APPLICATION NOTE ML5805 Register Programming Using the Three-Wire Serial Bus AN-096 RFMD Worldwide Applications Overview This application note presents typical ML5805 control logic and three-wire serial register signals captured with a logic analyzer.