REGISTER 1871 7 Search Results

Contextual Info: 2.0 Configuration Registers 2.1 OVERVIEW Nine registers constitute the Base Configuration Register set, and control the PC87323 setup. In general, these regis­ ters control the enabling of major functions FDC, UARTs, parallel port, pin functionalty etc. , the I/O addresses of

StatPro-150

Abstract: 29EE020 29EE512 a15 1334 28SF040 29EE010 228A10 STATPRO150
Contextual Info: Die Sales Specifications INTRODUCTION TO UNENCAPSULATED DIE This document provides the user with guidelines for processing, testing, and resolving applications issues associated with purchasing unencapsulated SST flash EEPROM die. Product electrical specifications, functional descriptions, and bonding diagrams are not included. This information is available in the appropriate

ic 4099

Abstract: 4099B 4099
Contextual Info: C O S /M O S S G S " TH<>I1S0N Q 7 C 1 I J13T237 IN T E G R A T E D f\ V Q 0 m l3 7 4 | H C C ,H C F 40998 "I C IR C U IT <tlC 0 8 9 5 1 7929225 Or T-46 -07-11 S G S S EM ICO N D U CT O R "cO R P 8-BIT ADDRESSABLE LATCH • • • • • • • • •

Contextual Info: 9.0 Keyboard Controller and Real-Time Clock The KBC is software compatible with the 8042AH industry standard keyboard controller as well as National’s PC87911. The PC87323 can execute code previously writ­ ten for an 8042 without further development. Unlike the

606-25

Abstract: 7812 voltage regulator spec. sheet SI5317A-C-GM panasonic 6169 1504 QFN GR-253-CORE JESD78 Si5315 SI5317B-C-GM SML-03
Contextual Info: Si5317 P I N - C ONTR OLLED 1 – 7 11 M H Z J I T T E R C LEANING C L O C K Features Ordering Information: Applications See page 40.  Data converter clocking  Wireless infrastructure  Networking, SONET/SDH Switches and routers  Medical instrumentation

Contextual Info: ¿ = 7 S C S -T H O M S O N *JÆ, 6aiD g ®IlL[I irMDȧ TS68951 MODEM RECEIVE ANALOG INTERFACE • TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION (WITH ASYNCHRO­ NOUS MULTIPLEXING OF 2 PLESIOCHRONOUS CHANNELS

Contextual Info: I S G S -T H O M S O N ¿ 5 7 TS68951 me MODEM RECEIVE ANALOG INTERFACE TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION with asynchronous multiplexing of 2 plesiochronous channels

EE60

Abstract: dc cdi schematic diagram ECHO schematic diagrams ts68950 vc-4095 DIP28 PLCC28 TS68951 TS68952 echo cancellation schematic diagram
Contextual Info: I S G S -T H O M S O N ¿ 5 TS68951 7 MODEM RECEIVE ANALOG INTERFACE TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION with asynchronous multiplexing of 2 plesiochronous channels PROGRAMMABLE SWITCHED CAPACITOR

Contextual Info: Si GEC PLESSEY S E M I C O N D U C T O R S VP2611 H.261 ENCODER Supersedes January 1996 Edition, DS3478 - 3.0 D E S C R IP TIO N FE A TU R E S Fully integrated H261 video encoder Up to full CIF resolution and 30 Hz frame rates Inputs YUV data in 8 x 8 sub block format

Contextual Info: VP2611 H.261 Encoder S E M IG O tV ID L IO lfO ß Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz fram e rates ■ Inputs YUV data in 8 x 8 sub block form at

VP510

Abstract: VP520 VP520S DS3487 H261 VP2611 VP2612 VP2614 VP2615 PAL colour coder block diagram
Contextual Info: VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

Contextual Info: VP2611 JANUARY 1996 ADVANCE INFORMATION DS3478 - 3.0 VP2611 H.261 ENCODER Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates

MACROBIOCK

Contextual Info: MITEL VP2611 _ H.261 Encoder QPvynrnMni inrm o Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz fram e rates ■ Inputs YUV data in 8 x 8 sub block form at

Contextual Info: J'îV ’ ' 31 G F C Pi FSSFY JUNE 1993 S l M I C: « N l U C T l) K S PRELIMINARY INFORMATION DS3478 • 1.4 VP 2611 H .261 ENCODER FEATURES DESCRIPTION I Fully integrated H261 video encoder H Up to full CIF resolution and 30 Hz frame rates H Inputs YUV data in 8 x 8 sub block format

DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S 1996 yuv rgb conversion frame buffer
Contextual Info: VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Contextual Info: Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ VP2611 VP2611

Contextual Info: 5.0 FDC Functional Description The PC87323 is software compatible with the DP8473 and 82077 floppy disk controllers. Upon a power on reset, the 16-byte FIFO will be disabled. Also, the disk interface out­ puts will be configured as active push-pull outputs, which

schematic diagram rca to usb

Abstract: LM317AT schematic usb to spi adapter AD1871 eval-adusb1 AD1941EB TDM8 db25 pcb AD1939 AD1940
Contextual Info: SigmaDSPTM 28-/56-Bit Audio Processor Evaluation Boards EVAL-AD1940EB/AD1941EB EVALUATION BOARD OVERVIEW PACKAGE CONTENTS This document explains the design and setup of the AD1940/AD1941 SigmaDSP evaluation boards. The AD1940EB/AD1941EB packages contain these items:

DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Contextual Info: VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

DS3487

Abstract: H261 VP2611 VP2612 VP2614 VP2615 VP510 VP520 VP520S
Contextual Info: VP2611 VP2611 H.261 Encoder Supersedes June 1996 edition, DS3487 - 4.0 DS3487 - 4.1 December 1998 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

Contextual Info: VP2611 @ M ITEL H.261 Encoder SE M IC O N D U C T O R Supersedes January 1996 edition, DS3487 - 3.0 DS3487 - 4.0 June 1996 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

gc132

Contextual Info: a i GEC PLESSEY SEPTEMBER 1994 PRELIMINARY INFORMATION S E M I C O N D U C T O R S DS3478 - 2.3 VP2611 H.261 ENCODER Supersedes version in December 1993 Digital Video & DSP 1C Handbook, HB3923-1 DESCRIPTION FEATURES Fully integrated H261 video encoder Up to full CIF resolution and 30 Hz frame rates

Contextual Info: M ITEL VP2611 _ H.261 Encoder SE M IC O N D U C T O R Supersedes January 1996 edition, DS3487 - 3.0 DS3487 - 4.0 June 1996 FEATURES DESCRIPTION • Fully integrated H261 video encoder ■ Up to full CIF resolution and 30 Hz frame rates ■ Inputs YUV data in 8 x 8 sub block format

68951

Abstract: TS68951 BAT43 equivalent RC6 philips DIP28 PLCC28 TS68950 TS68951CFN TS68951CP TS68952
Contextual Info: TS68951 MODEM RECEIVE ANALOG INTERFACE . . . . . . . TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION WITH ASYNCHRONOUS MULTIPLEXING OF 2 PLESIOCHRONOUS CHANNELS PROGRAMMABLE SWITCHED CAPACITOR