R6B RECEIVER Search Results

ECT1-1-13

Abstract: ETC1-1-13 Analog Devices T1B ERJ6GEYJR00V ferrite sheet panasonic ERJ6GEYJR00V PANASONIC C10A ERJ6GEYJ100V TC4-1W c13b
Contextual Info: AD8343 Evaluation Board EVAL-AD8343EB BOARD DESCRIPTION The AD8343 Evaluation Board has two independent areas, denoted A and B. The circuit schematics are shown in Figures 1 and 2. An assembly drawing is included in Figure 3 to ease identification of components, and representations of the board layout are included

AV TO VGA CONVERTER circuit

Abstract: VGA TO AV CONVERTER circuit MAX2980 homeplug AV to VGA converter EN30U 6600CS Sumitomo 6600CS
Contextual Info: Preliminary Data Sheet MAX2980 MAX2980 HomePlug Analog Front End Power Line Interface Features: HomePlug Analog Front End including ADC, DAC, filters, and line driver for power line communications. • Fully Integrated Line Driver and Receiver • Seamless Interface to Digital

MAX2982

Abstract: MAX2981 MAX2980 aec-q100-rev-F powerline carrier transmission MAX2986 R1B14 MAX2982 pcb programming max2982 R3B7
Contextual Info: 19-4736; Rev 0; 7/09 Integrated Powerline Communication Analog Front-End Transceiver and Line Driver Features The MAX2981 powerline communication analog frontend AFE and line-driver IC is a state-of-the-art CMOS device that delivers high performance at low cost. This

MAX2980

Abstract: powerline communication homeplug Powerline Alliance AC powerline
Contextual Info: 19-3534; Rev 0; 1/05 Powerline Communication Analog Front-End Transceiver The MAX2980 powerline communication analog frontend AFE integrated circuit (IC) is a state-of-the-art CMOS device that delivers high performance and low cost. This highly integrated design combines an analogto-digital converter (ADC), digital-to-analog converter

balun LDB20C

Abstract: ERJ6GEYJR00V Z5B Series
Contextual Info: DC to 2.5 GHz High IP3 Active Mixer Preliminary Technical Data FEATURES High Performance Active Mixer Broadband Operation to 2.5 GHz Conversion Gain: +7.1 dB Input IP3: +16.5 dBm LO Drive: -10 dBm Noise Figure: 12.5 dB Input P1dB: +2.8 dBm Differential LO, IF and RF Ports

AD8343ARUZ

Abstract: LQW1608A tektronix 2230 AD8343 BLM21P300S C10A C10B C11A C11B HP8130
Contextual Info: DC-to-2.5 GHz High IP3 Active Mixer AD8343 High-performance active mixer Broadband operation to 2.5 GHz Conversion gain: 7 dB Input IP3: 16.5 dBm LO drive: –10 dBm Noise figure: 14 dB Input P1dB: 2.8 dBm Differential LO, IF and RF Ports 50 Ω LO input impedance

LDB20C

Abstract: ECT1-1-13 ERJ6GEYJR00V PANASONIC murata MA188R2J MA180R4B tektronix 2230 AD8343 AD8343ARU AD8343ARU-REEL AD8343ARU-REEL7
Contextual Info: a FEATURES High-Performance Active Mixer Broadband Operation to 2.5 GHz Conversion Gain: 7.1 dB Input IP3: 16.5 dBm LO Drive: –10 dBm Noise Figure: 14.1 dB Input P1 dB: 2.8 dBm Differential LO, IF and RF Ports 50 ⍀ LO Input Impedance Single-Supply Operation: 5 V @ 50 mA Typical

Contextual Info: DC-to-2.5 GHz High IP3 Active Mixer AD8343 High-performance active mixer Broadband operation to 2.5 GHz Conversion gain: 7 dB Input IP3: 16.5 dBm LO drive: –10 dBm Noise figure: 14 dB Input P1dB: 2.8 dBm Differential LO, IF and RF Ports 50 Ω LO input impedance

MAX13175E

Abstract: RS-423 RS-449 RS-530A
Contextual Info: 19-4595; Rev 3; 8/11 KIT ATION EVALU E L B A IL AVA Multiprotocol, Pin-Selectable Data Interface Chipset Features ♦ Supports V.28 RS-232 , V.10 (RS-423), V.11 (RS-449/V.36, RS-530, RS-530A, X.21) and V.35 Protocols The MAX13171E along with the MAX13173E/

RS-530A

Abstract: M13516 MAX13171EETU MAX13175e R5B transistor rs-422 db25 cables
Contextual Info: 19-4595; Rev 1; 7/09 Multiprotocol, Pin-Selectable Data Interface Chipset Features ♦ Supports V.28 RS-232 , V.10 (RS-423), V.11 (RS-449/V.36, RS-530, RS-530A, X.21) and V.35 Protocols The MAX13171E along with the MAX13173E/ MAX13175E, form a complete pin-selectable data terminal equipment (DTE) or data communication equipment

Contextual Info: 19-4595; Rev 3; 8/11 KIT ATION EVALU E L B A IL AVA Multiprotocol, Pin-Selectable Data Interface Chipset Features ♦ Supports V.28 RS-232 , V.10 (RS-423), V.11 (RS-449/V.36, RS-530, RS-530A, X.21) and V.35 Protocols The MAX13171E along with the MAX13173E/

r6b receiver

Contextual Info: LTC1344A TECHNOLOGY Software-Selectable C able Terminator F6RTUR6S D€SCRIPTIOn Software-Selectable Cable Termination for: RS232 V.28 RS423 (V.10) RS422 (V.11) RS485 RS449 EIA530 EIA530-A V.35 V.36 X.21 » Outputs Won’t Load the Line with Power Off The LTC 1344A features six software-selectable

100MF 35v

Abstract: application of wattmeter 86H-7071 smd 1a 100v diode bridge DIODE SMD 1206 philips make 150mF capacitor 400V D1N4937 SMD 1218 capacitor SFH6156-2T diode d1n4148
Contextual Info: AND8288/D NCP1351 Evaluation Board, a 12 V / 2 A Full DCM Adapter Prepared by Stéphanie Conseil http://onsemi.com This application note describes a 12 V / 2 A simple adapter operated by NCP1351, a fixed on- time / variable off-time controller. This adapter features a very low standby power below 90

HP8130

Abstract: LDB20C murata MA188R2J AD8343 AD8343ARU AD8343ARU-REEL AD8343ARU-REEL7 AD8343-EVAL HP8648C RU-14
Contextual Info: a FEATURES High-Performance Active Mixer Broadband Operation to 2.5 GHz Conversion Gain: 7.1 dB Input IP3: 16.5 dBm LO Drive: –10 dBm Noise Figure: 14.1 dB Input P1 dB: 2.8 dBm Differential LO, IF and RF Ports 50 ⍀ LO Input Impedance Single-Supply Operation: 5 V @ 50 mA Typical

phase detector AD8302

Contextual Info: a RF/IF Gain and Phase Detector Preliminary Data Sheet AD8302 FEATURES M easures Gain/Loss and Phase from LF to 3 GHz Dual Demodulating Log Amps and Phase Dete ctor Input Range –6 2 dBm to –2 dBm in 50 Ω S ys tem Ac cur ate G ain M easurement Scaling 30 mV/dB

Contextual Info: Final E lectrical S p e cifica tio n s r r LTC1344 TECHNOLOGY u n w i Software Selectable Cable Terminator August 1996 F€ A TU R € S DCSCRIPTIOn • Software Selectable Cable Termination tor: RS232 V.28 RS423 (V.10) RS422 (V.11) RS485 RS449 EIA530 EIA530-A

Contextual Info: a iL R E L E A S E Final E le ctrica l S p e c ific a tio n s L i n t i A R LTC1344A . TECHNOLOGY Soft w a re -Se Ie c t a b Ie C a b le T erm inator February 1998 F€RTUR€S DCSCRIPTIOn • Software-Selectable Cable Termination for: RS232 V.28 RS423 (V.10)

Contextual Info: DATASHEET ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function Description Features/Benefits 1-to-2 Zero-delay or fanout buffer for PCI Express.The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC

V11 interface

Contextual Info: L iim TECHNOLOGY Final Electrical S pecifications LTC1344A Software-Selectable C able Terminator F e b ru a ry 1998 FCATURCS DCSCRIPTIOfl • Software-Selectable Cable Termination for: RS232 V.28 RS423 (V.10) RS422 (V.11) RS485 RS449 EIA530 EIA530-A V.35

Contextual Info: DATASHEET ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function Description Features/Benefits 1-to-2 Zero-delay or fanout buffer for PCI Express.The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC

932S421BGLF

Abstract: ICS9DB102 ICS952601 ICS954101
Contextual Info: DATASHEET ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function Description Features/Benefits 1-to-2 Zero-delay or fanout buffer for PCI Express.The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC

Contextual Info: IM T D ^ L ^ E L E M dE Final Electrical Specifications / r u LTC1344 m TECHNOLOGY Software S electable C a b le Terminator August 1996 F€flTUR€S DCSCftlPTIOn • Software Selectable Cable Termination for: RS232 V.28 RS423 (V.10) RS422 (V.11) RS485 RS449

9DB102YGLFT

Contextual Info: DATASHEET ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function Description Features/Benefits 1-to-2 Zero-delay or fanout buffer for PCI Express.The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC

9DB102

Abstract: 9DB102BFLF
Contextual Info: DATASHEET ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Description Features/Benefits The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main