R3010 MIPS PROCESSOR Search Results

arinc 629 controller

Abstract: arinc 629 79c900 MIPS R3000A R3000 mips VRTX32 R3052 R4400 ortec R3000
Contextual Info: Evaluation Boards Creative Electronics Systems S.A. RAID 8235 Standard Features ❑ R3000 MIPS RISC processor 24 MHz , R3010 FPU, 128 Kbytes independent data & instruction caches, 4 up to 32 Mbytes on-board system memory DRAM ❑ SCSI, Ethernet, 2 x RS 232C

arinc 629

Abstract: arinc 629 controller VME COnnector 79C900 MIL-1553 96 pin vme DIN connector MIPS R3000A VME pci R3000 mips din 6900
Contextual Info: Evaluation Boards Creative Electronics Systems S.A. RAID 8235 Standard Features ❑ R3000 MIPS RISC processor 24 MHz , R3010 FPU, 128 Kbytes independent data & instruction caches, 4 up to 32 Mbytes on-board system memory DRAM ❑ SCSI, Ethernet, 2 x RS 232C

R3000 mips

Abstract: MIPS R3000 MIPS R3000 fpu idt r3000 mips risc architecture gerry kane R3000 R3051 R3052 R3081 R3500
Contextual Info: IDT7S930 IDT/c RISController C-COMPILER PRODUCT BRIEF  IDT/c Multi-Host GNU C-Compiler System IDT7S930 Integrated Device Technology, Inc. OPTIMIZING C-COMPILER SYSTEM: FEATURES: • ANSI C-Compliant GNU Compiler, Assembler, Linker, Librarian, and ANSI Libraries

MIPS r3000

Abstract: mips risc architecture gerry kane mips r4600 R3000 mips AR3010 R3000 R3051 R3052 R3081 R3500
Contextual Info: IDT7S930 IDT/c RISController C-COMPILER PRODUCT BRIEF IDT/c Multi-Host GNU C-Compiler System IDT7S903 Integrated Device Technology, Inc. FEATURES: OPTIMIZING C-COMPILER SYSTEM: • ANSI C-Compliant GNU Compiler, Assembler, Linker, Librarian, and ANSI Libraries

TAG 9031

Abstract: mips r3000 pin diagram R3000 processor R3010 mips processor R3000 7RS102 mips r3010 r3000 idt 7RS110 U/25/20/TN26/15/850/Triac TAG 9031
Contextual Info: jfflPN R3000 CPU MODULES FOR COMPACT SYSTEMS }e & IDT7RS102 Integrated Device Technology, Inc. R3000 MODULE FOR GENERAL USE IN SMALL SYSTEMS: FEATURES: • Cache Size: 16K Instruction, 16K Data The IDT7RS102 is a complete reduced instruction set computer RISC) CPU, based on the MIPS R3000 RISC

7RS110

Abstract: AR3010 mips r3000 pin diagram R3010 mips processor 7RS110N55A33A 7RS110F54A25A 7RS310 R3000A IDT7RS110 res 3010
Contextual Info: IDT7RS110 PLUG COMPATIBLE FAMILY OF R3000 CPU MODULES Integrated Device Technology, Inc. FEATURES: • C hoice o f Cache Sizes: 32 I and D o r 32K I and 16K D R3000 MODULE FOR GENERAL USE IN SMALL SYSTEMS: The IDT7RS110 is a com plete reduced instruction set

IDT7RS101

Abstract: MIPS R3000A R3000A mips r3000 pin diagram 7RS301 R3010 mips processor R3000 mips
Contextual Info: IDT7RS101 R3000 CPU MODULES FOR GENERAL APPLICATIONS Integrated Device Technology, Inc. FEATURES: POWERFUL GENERAL PURPOSE R3000 MODULE: • R3000 CPU on 3.7" x 6.5" plug-ln module • 64K each Instruction and Data Caches • On-board clock generation • Four-word read buffer for block refill. Single

R3000A

Abstract: mips r3000 pin diagram P9103 R3000 R3010A Integrated Device Technology r3000 instruction clock cycle R3010 mips processor R3010A MIPS R3000A R3000 processor
Contextual Info: IDT7RS103 R3000 CPU MODULES FOR COMPACT SYSTEMS In te g ra te d D evice T echnology, Inc. DISTINCTIVE FEATURES: • Three Cache Size Versions: 16K Instruction, 16K Data 7RS103-44 32K Instruction, 32K Data (7RS103-55) 64K Instruction, 64K Data (7RS103-66)

SN2681

Abstract: mips r3000 pin diagram R3001 R3010 mips processor SCN2681 3 pins Variable resistor 10K ohm Sn268 PB-104
Contextual Info: SP'X R3001 RISC ENGINE FOR EMBEDDED CONTROLLERS Jdfj ADVANCE INFORMATION IDT7RS104 Integrated De>rice Technology, Inc. R3001 MODULE WITH SYNCHRONOUS MEMORY FEATURES: • 128K each of Instruction and Data RAM In Synchronous Memory • Simple Interface to peripherals

Contextual Info: * 4 A M A A PaceMipsR3010 32-Bit, 25 MHz RISC Floating Point Accelerator a P E fíF O R M 4N C E fa fS fM C O /V D i/C rO /f CORPOfíAT/O/V Means Quality, Service and Speed 1989 Performance Semiconductor Corporation 7$ — — TABLE OF CONTENTS Features and Description. 6-109

R3010

Abstract: fpa g12 burndy C1989 PR3000 R2010 R3000 R2010 mips processor mips r3010
Contextual Info: P ñ E L m m & w ? A PaceM ipsR3010 A 32-Bit, 25 MHz RISC A *4 Floating Point A Accelerator E PERFORM4/VCE Means Quality, Service and Speed S£M /C O A/D U C rO ft C O ftP O ffA n O A f 6-107 This Material Copyrighted By Its Respective Manufacturer 01969 Perfor manes Semiconductor Corporation

R3000A

Abstract: mips r3000 pin diagram R3010 mips processor MIPS R3000A
Contextual Info: Integrated Device Technology* Inc. R3000 CPU MODULES FOR HIGH PERFORMANCE AND MULTIPROCESSOR SYSTEMS FEATURES: • Cache Size: 64K Instruction, 64K Data • Processor Speeds up to 33 MHz • Includes R3010 Floating Point Accelerator • 1-word Read Buffer; 4-word Write Buffer

R2010A

Abstract: R3010 mips processor mips r2000a CERPAK PR2000
Contextual Info: PaceMips R2010A FPA 32-BIT RISC CO-PROCESSOR FLOATING POINT ACCELERATOR ¡ P ^ iL D U D IN Iñ ^ V ySf~ FEATURES Produced with PACE il Technology™ Tightly-coupled Interface with the PaceMips R2000A Increases system performance: - 5 MFLOPS for single precision and 3 MFLOPS

CERPAK

Abstract: R3010 mips processor mips r3010 mips r2000a PR2000
Contextual Info: PaceMips R2010A FPA 32-BIT RISC CO-PROCESSOR FLOATING POINT ACCELERATOR p œ y iM lO IN lM â Y FEATURES Produced with PACE li Technology™ Tightly-coupled Interface with the PaceMips R2000A Increases system performance: - 5 MFLOPS for single precision and 3 MFLOPS

Contextual Info: RISCore RISC CPU PROCESSOR PRELIMINARY IDT79R3500A Integrated Device Technology, Inc. FEATURES: • A single chip integrating the R3000 CPU and R3010 FPA execution units, using the R3000A pinout. • Efficient Pipelining— The CPU's 5-stage pipeline design

Contextual Info: IN T E GR AT ED 3AE D DEVIC E • 4 Ô 2 S 77 1 0 Q 0 7 b S b M ■ IDT _ T-M9-17- 2>2~ RISCore RISC CPU PROCESSOR PRELIMINARY IDT79R3500A Integrated Device Technology, Inc. FEATURES: Supports independent multiword block refill of both the

R4000MC

Abstract: R2000 mips Siemens R2000 R4000SC R2010 mips processor R3010 mips processor MIPS R3000A mips r4000 block diagram R2000 mips processor
Contextual Info: 5 3 0 lJâ04 ODIO'îTB D5fl « L L C Introduction to the LR4000 MIPS Microprocessor Publication ID: J 1 4 0 1 5 Publication D ate: O cto b er 1, 1 9 9 1 Company: L S I LOGIC CORP This title page is provided as a service by In fo rm a tio n Handling Services and displays

R3010

Abstract: 79r3010 MIPS R2000 79r3000 MIPS R2000 cache R2000 R3000 R3000A R3500A CFC-1
Contextual Info: RISCore RISC CPU PROCESSOR PRELIMINARY IDT79R3500A Integrated Device Technology, Inc. FEATURES: • • • • • • • Supports independent multiword block refill of both the instruction and data caches with variable block sizes. Supports concurrent refill and execution of instructions.

LR33050

Abstract: LR33050HC25 LR33000 R2010 mips processor R3010 mips processor AX2016 LR33050HC40 R2000 mips R2000 mips processor Enhanced Self-Embedding Processor Core
Contextual Info: LSI LOGIC LR33050 MIPS IFX Processor Preliminary Introduction The LR33050 M IP S IFX Integer and FloatingPoint A cce le rato r P ro ce sso r is part of LSI Logic's LR33000 M IP S Self-Em bedding pro­ ce sso r family. The LR33050 is a 32-bit Reduced Instruction Set Computer (R ISC ) p rocessor that

mips r3010

Abstract: PR3000A R3010 mips processor
Contextual Info: PaceMips" PR3010A FPA 32-BIT RISC CO-PROCESSOR FLOATING POINT ACCELERATOR ¿ s- FEATURES • 32-BIT RISC Co-Processor: - Contains thirty-two 32-bit registers or sixteen 64-bit registers to support Single-Precision or

Contextual Info: PaceMips PR4000PC CPU advance information 64-BIT THIRD GENERATION RISC PROCESSOR WITH MMU, FPA, & PRIMARY CACHES FEATURES • Superpipelined FPA: - 32/16 en try 32/64 b it re g iste r file in a 32-bit mode - 32 entry 64-bit register file in 64-bit mode

Contextual Info: PaceMips PR4000PC CPU a d v a n c e in fo 64-BIT THIRD GENERATION RISC PROCESSOR WITH MMU, FPA, & PRIMARY CACHES FEATURES • Superpipelined FPA: - 32/16 en try 32/64 b it reg ister file in a 32-bit mode - 32 entry 64-bit register file in 64-bit mode - S upports single & double precision

Contextual Info: Pace Mips PR3010A FPA 32-BIT RISC CO-PROCESSOR FLOATING POINT ACCELERATOR FEATURES • 32-BIT RISC Co-Processor: - Contains thirty-two 32-bit registers or sixteen 64-bit registers to support Single-Precision or Double-Precision Arithmetic ■ Fully conforms to requirements of ANSI/IEEE

MQUAD

Abstract: R3500 mips r2000 cache r2000 processor tag27 IDT79R3000 IDT79R3500 R2000 R2010 R3000
Contextual Info: IDT79R3500 RISC CPU PROCESSOR RISCore  MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT79R3500 RISC CPU PROCESSOR RISCore Integrated Device Technology, Inc. • Supports concurrent refill and execution of instructions. • Partial word stores executed as read-modify-write.