QS59920 Search Results

Contextual Info: pyi Low Skew Tm\ ^ QS59920 PLL Clock Driver Sem iconductor, Inc. T u rb o Q o c K ' p r e l im in a r y J r . FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge synchronization

Contextual Info: 1 Q uality Semiconductor , I nc . QS59910 QS59920 Low Skew PLL Clock Driver TurboClock Jr. FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Selectable positive or negative edge synchronization • Synchronous output enable • Output frequency: 15MHz to 110MHz

AN-45

Abstract: AN-46 QS5919 QS5991 QS5992 QS5993 QS5V991 QS5V993 1-22Mhz Phase Frequency detector
Contextual Info: AN-46 Q QUALITY SEMICONDUCTOR, INC. Frequently Asked Questions FAQ About QSI Phase-Locked Loops The following is a list of the most commonly asked questions about QSI phase-locked loop (PLL) clock drivers. The following answers provide a brief explanation to each question. More complete explanations to some of the questions in this application note

L0107

Abstract: IDTQS5V993-5QI L-01-07
Contextual Info: Integrated Device Technology, Inc. 2975 Stender Way, Santa Clara, CA - 95054 Phone #: 408 727-6116 Fax #: (408) 727-2328 PRODUCT DISCONTINUANCE NOTICE (PDN) PDN #: L-01-07 Issue Date: July 30, 2001 Last Buy Date: July 28, 2002 October 28, 2002 Last Ship Date:

Contextual Info: L0WSkew PLL Clock Driver S5992S advance T u rb O d O C k " J r. Q u a lit y S e m ic o n d u c t o r , I n c . INFORMATION FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge