QEL 150 Search Results

ISPSD coolmos

Abstract: bup400d mosfet nepi
Contextual Info: Properties of the New Compensation Devices CoolMOS between 420K and 80K— the Ideal Device for Cryogenic Applications* A.E. Schlögl a), G. Deboy b), H.W. Lorenzen c), U. Linnert a), H.-J. Schulze a) and J.P. Stengl b) a) SIEMENS AG, Corporate Technology, Research Center Power Electronics, Otto-Hahn-Ring 6, 81730 Munich, Germany

Contextual Info: SILICON MONOLITHIC Bi-CMOS INTEGRATED CIRCUIT TD6338P Bi-CMOS 10 BIT SERIAL-INPUT /PARALLEL OUTPUT DRIVER The TD6338P is an IC built using a B i-C M O S process characterized by high output w ithstand voltage. It contains a serial-input, 10-stage parallel-output shift

PI0512WSN

Abstract: PI0128WSN 9 ELEMENT photoDIODE ARRAY PI0256WSN
Contextual Info: Peripheral Imaging Corporation PI0128WSN, PI0256WSN, PI0512WSN 50-mm-Pitch Wide Aperture Spectroscopic Photodiode Arrays Engineering Data Sheet Description Peripheral Imaging Corporation's WSN series is family of self-scanning photodiode solid-state linear imaging

Contextual Info: •H Y UN D A I H Y 6 2 2 5 6 A S e r ie s 32Kx 8-bit CMOS SRAM DESCRIPTION The HY62256A is a high-speed, low power and 32,768 x 8-bits CMOS static RAM fabricated using Hyundai's high performance twin tub CMOS process technology. This high reliability process coupled with innovative circuit

M74LS138P

Abstract: M74LS137P 20-PIN demultiplexer containing latch 1329T
Contextual Info: MITSUBISHI LSTTLs M74LS137P 3-LINE-TO -8-LINE DECODER/DEMULTIPLEXER W ITH ADDRESS LATCH DESCRIPTION The M 7 4L S 13 7P is a semiconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW taining a 3-line-to-8-line decoder/m ultiplexer function w ith address latch.

S18A

Contextual Info: LOGIC D E V I C E S INC SfcsE D • SSbSIDS 0001253 4 ■ _ _ ;_ ;_ T - 9 S - LMU18 16 x 16-bit Parallel Multiplier DESCRIPTION □ 35 ns Worst-Case Multiply Time Q Low Power CMOS Technology

UCC2895

Abstract: OVERCURRENT LIMITING IN UCC3895 UCC3895 power supply application UCC3895
Contextual Info: UCC1895 UCC2895 UCC3895 UNITRO IDE BiCMOS Advanced Phase Shift PWM Controller PRELIMINARY FEATURES DESCRIPTION • Programmable Output Turn-on Delay The UCC3895 is a phase shift PWM controller that implements control of a full-bridge power stage by phase shifting the switching of one half-bridge

Contextual Info: TO SH IBA TC55V400FT/TR/XB-70,-85,-10 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55V400FT/TR/XB is a 4,194,304-bit static random access memory SRAM organized as 262,144 words

B37472

Abstract: epcos
Contextual Info: Multilayer ceramic capacitors Chip, X8R Series/Type: Chip Date: February 2009 EPCOS AG 2009. Reproduction, publication and dissemination of this publication, enclosures hereto and the information contained therein without EPCOS' prior express consent is prohibited.

Contextual Info: Multilayer ceramic capacitors Chip, HQF Series/Type: Chip Date: February 2009 EPCOS AG 2009. Reproduction, publication and dissemination of this publication, enclosures hereto and the information contained therein without EPCOS' prior express consent is prohibited.

LM3909 equivalent

Abstract: transistor KJJ LM2925 LM3909 L4947 LM2926 LM2926T LM2927 LM2927T T05A
Contextual Info: a t i o n a l S e m i c o n d u c t o LM2926/LM2927 N r LM2926/LM2927 Low Dropout Regulator with Delayed Reset General Description The LM2926 is a 5V, 500 mA, low dropout regulator with delayed reset. The microprocessor reset flag is set low by thermal shutdown, short circuits, overvoltage conditions,

ic hip4082 pin diagram

Abstract: hip4082 HIP4082IP pump motor
Contextual Info: HIP4082 fH HARRIS S E M I C O N D U C T O R 80V, 1.25A Peak Current H-Bridge FET Driver March 1995 Description Features Independently Drives 4 N-Channel Bridge or Full Bridge Configurations The HIP4082 is a medium frequency, medium voltage H-Bridge N-Channel MOSFET driver IC, available in 16 lead plastic SOIC

B37940

Contextual Info: Multilayer ceramic capacitors Chip, C0G Series/Type: Chip Date: February 2009 EPCOS AG 2009. Reproduction, publication and dissemination of this publication, enclosures hereto and the information contained therein without EPCOS' prior express consent is prohibited.

Contextual Info: Multilayer ceramic capacitors Chip, X7R Series/Type: Chip Date: February 2009 EPCOS AG 2009. Reproduction, publication and dissemination of this publication, enclosures hereto and the information contained therein without EPCOS' prior express consent is prohibited.

33D10

Abstract: A4t 3m 3 pin DDD22 S2042B-05 1010 OEI YAT-6
Contextual Info: PRELIMINARY DEVICE SPECIFICATION >9MCC HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS FEATURES • Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards • S2042 transmitter incorporates phase-locked loop PLL providing clock synthesis from lowspeed reference

TF-128

Abstract: O031
Contextual Info: I =1? ip £ 3 - 4 i yc 1 il c P>T ps UHHMifht - IJ* 1 4 \k * Q eroflex Cl RCUITTBCHNOLOGY Features • 4 Low Power 128K x 8 FLASH Die in One MCM Package ■ Organized as 128K x 32 • User Configurable to 256K x 16 or 512K x 8 • Upgradable to 512K x 32 in same Package Style

hcn 73

Abstract: CY7C09099V
Contextual Info: fax id: 521 0 V CYPRESS CY7C09079V/89V/99V CY7C09179V/89V/99V PRELIMINARY 3.3V 32K/64K/128K x 8/9 Synchronous Dual Port Static RAM Features • 0.35-m icro n C M O S fo r o ptim u m sp ee d /p o w e r • H ig h-speed clo ck to d ata ac c e s s 10/12 ns m ax.

D501

Abstract: B37741 k1060 smd tabellen Siemens Matsua Components Bestellnummern-Verzeichnis K0682 d5050 nf schaltungen NDKM B37872
Contextual Info: Inhaltsverzeichnis Bestellnummernverzeichnis Seite 5 8 Lieferübersicht Elektrische Kurzdaten 11 26 Standard-Chip-Kondensatoren Slim-Line Kondensatoren 27 55 Bedrahtete Kondensatoren, EIA-Standard Bedrahtete Kondensatoren, CECC-Standard 59 68 Allgemeine technische Angaben

"32K x 8" dual port SRAM PLCC

Contextual Info: fax id: 5212 V CYPRESS C Y 7 C 1 3 8 V /1 4 4 V /0 0 6 V /0 0 7 V PRELIMINARY C Y 7 C 1 3 9 V /1 4 5 V /0 1 6 V /0 1 7 V 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Features • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/

hcn 73

Contextual Info: fax id: 5211 V CYPRESS CY7C09269V/79V/89V CY7C09369V/79V/89V PRELIMINARY 3.3V 16K/32K/64K x 16/18 Synchronous Dual Port Static RAM Features • H ig h-speed clo ck to d ata ac c e s s 10 /12ns m ax. • 3.3V Low o p e ratin g p o w er • True D u al-P o rted m e m o ry cells w h ich allo w sim u lta­

Contextual Info: HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM IDT7130SA/LA IDT7140SA/LA In te g ra te d D e v i s le c h n o J o g y , l i e . FEATURES 1 6-o r-m o re-b its using S L A V E ID T 7 1 4 0 • H ig h -s p e ed ac cess — M ilitary: 2 5 /3 5 /5 5 /1 0 0 n s m a x.

TCD1250D

Abstract: tcd1250 CCD linear array LM4041 LM9800 LM9800CCV LM9800CCVF V52A RGB signal converting to vga
Contextual Info: August 1995 S e mi c o n d u c t o r LM 9800 8-B it G re y s c a le /2 4 -B it C o lor Linear CCD S ensor P rocessor General Description Features The LM9800 is a high performance integrated signal proc­ essor/digitizer for linear CCD image scanners. The LM9800

TMS34061FNL

Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
Contextual Info: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW

SPVB066C

Abstract: TMS34010 TMS340SDK-PC spvu SPVU001 SPVU001B t4035
Contextual Info: TMS34010 GRAPHICS SYSTEM PROCESSOR SPVS002C - • Instruction - 132 ns - 160 ns - 200 ns Cycle . . . TOP VIEW r- ^ Fully Programmable 32-Bit General-Purpose Processor with 128-Megabyte Address Range • Pixel Processing, XY Addressing, and Window Checking Built into the Instruction