QB3 300 Search Results

300GA

Contextual Info: page 1 2 QB3/300GA sheet 1 FP date 1960.07.07 2000.01.15

QB3/300

Abstract: qb3-300 QB3 300
Contextual Info: page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 QB3/300 sheet 1 2 3 3 4 4 5 6 7 8 A B C D E F G H I date 1954.07.07 1954.07.07 1959.03.03 1960.09.09 1959.03.03 1960.09.09 1956.03.03 1956.03.03 1954.07.07 1954.07.07 1958.06.06 1958.06.06 1958.06.06 1958.06.06

CAT64LC10

Abstract: QDD173C1
Contextual Info: b öE l'ib S b 'îS D DDQ1 7 3 b Qb3 « C S T IIHICRTRLY5T C A T A L Y S T SEMICONDUCTOR • Iff / A d va n c e S E M I C O N D U C T O R CAT64LC10/CAT64LC1 Ol 1K-Bit SERIAL E2PROM FEATURES ■ S P I B u s C o m p atib le P o w er-U p In a d v e rtan t W rite P rotectio n

QB3 300

Abstract: 2X15W 2X63 2X163 class B amplifier qb3-300
Contextual Info: Q B 3 /30 0 6155 y V. R.F. POWER TETRODE Products approved to CECC 45 003-008. QUICK REFERENCE DATA X 2,5 2,5 2,5 2,5 2 1,5 freq. B teleph. C telegr. B mod. * c ag2 mod. MHz va V w0 w va V w0 w va V w0 w va V w0 w 120 120 120 120 150 200 3000 2500 2000 1500

2X63

Abstract: septar socket qB3 200 7Z00 philips SQ 10 amplifier 2X14 2X15 2X40 QB3 300
Contextual Info: PHILIPS QB 3/200 TETRODE for use as R.F. or A.F. amplifier TÉTRODE pour utilisation comme amplificatrice H.F. ou B.F. TETRODE zur Verwendung als HF- oder NF-Verstärker Cooling : radiation/low velocity air flow Refroidissement: radiation/léger courant d'air

top mark QA1

Abstract: MAX9317 9317A MAX9317A MAX9317AETJ MAX9317ECJ MAX9317ETJ MC100EP210S
Contextual Info: 19-2543; Rev 0; 7/02 Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs Features The MAX9317/MAX9317A/MAX9317B/MAX9317C lowskew, dual 1-to-5 differential drivers are designed for clock and data distribution. The differential input is reproduced at five LVDS outputs with a low output-tooutput skew of 5ps.

Contextual Info: 19-2543; Rev 0; 7/02 Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs Features The MAX9317/MAX9317A/MAX9317B/MAX9317C lowskew, dual 1-to-5 differential drivers are designed for clock and data distribution. The differential input is reproduced at five LVDS outputs with a low output-tooutput skew of 5ps.

0430700000

Abstract: 0430500000 Fuse 0430900000 9503330000 04-3070-0000 043050
Contextual Info: Circuit Protection Terminals KDKS 1 with power on indication combi-foot Warning: • Install AP partition after last ASK 1 or KDKS 1. • Disconnect power before replacing the fuse. Fuse terminals are available with LED blown fuse indicators, which speed identification of fuse failures

Contextual Info: Freescale Semiconductor, Inc. Order number: MPC9315 Rev 3, 08/2004 TECHNICAL DATA 2.5V and 3.3V CMOS PLL Clock Generator and Driver The MPC9315 is a 2.5V and 3.3V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to

043060000

Abstract: 0431100000
Contextual Info: Circuit Protection Terminals KDKS 1 with power on indication with blown fuse indicator BFI and circuit disconnect Warning: • Install AP partition after last ASK 1 or KDKS 1. • Disconnect power before replacing the fuse. Fuse terminals are available with

33740

Abstract: 337-40 blown fuse indicator 9134531111
Contextual Info: Circuit Protection Terminals KDKS 1 with power on indication combi-foot Warning: • Install AP partition after last ASK 1 or KDKS 1. • Disconnect power before replacing the fuse. Fuse terminals are available with LED blown fuse indicators, which speed identification of fuse failures

Contextual Info: Freescale Semiconductor, Inc. Order number: MPC9315 Rev 3, 08/2004 TECHNICAL DATA 2.5V and 3.3V CMOS PLL Clock Generator and Driver The MPC9315 is a 2.5V and 3.3V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to

Contextual Info: 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver MPC9315 NRND DATASHEET NRND – Not Recommend for New Designs The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. The

MAX9312

Abstract: MAX9312ECJ MAX9312EGJ MAX9312EHJ MAX9314 MAX9314ECJ MAX9314EGJ MC100EP210 MC100LVEP210
Contextual Info: 19-2079; Rev 1; 2/02 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential

MAX9312

Contextual Info: 19-2079; Rev 2; 4/09 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential

TF121

Abstract: MAX9312
Contextual Info: 19-2079; Rev 0; 8/01 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers Features ♦ +2.25V to +3.8V Differential HSTL/LVPECL Operation ♦ -2.25V to -3.8V Differential LVECL Operation ♦ 30ps typ Part-to-Part Skew ♦ 12ps (typ) Output-to-Output Skew

Contextual Info: 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver MPC9315 NRND DATASHEET NRND – Not Recommend for New Designs The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. The

QC140

Abstract: AN1091 MPC9315
Contextual Info: DATA SHEET MPC9315 Freescale Semiconductor Technical Data Rev. 4, 08/2005 2.5 V and 3.3 V CMOS PLL Clock 2.5 V and V CMOS PLL Clock Generator and 3.3 Driver Generator and Driver The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to

MAX9312

Abstract: JESD51-7 MAX9312ECJ MAX9314 MAX9314ECJ MC100EP210 MC100LVEP210 TQFN-ep 20 pcb footprint
Contextual Info: 19-2079; Rev 2; 4/09 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers Features The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential

qb3-300

Abstract: QB3 300 tetrode
Contextual Info: PHILIPS QB 3/300 GA TETRODE for use as H.F. or L.F. amplifier TETRODE pour utilisation en amplificatrice H.F. ou B.F. TETRODE zur Verwendung als HF- oder NF-Verstärker Dimensions in mm Dimensions en mm Atmessungen in mm Base : lietal-shell Giant 5p. Culot : Giant 5p. avec culot métallique

Contextual Info: 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver ICS843N001I NRND DATASHEET NRND – Not Recommend for New Designs The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to

AN1091

Abstract: MPC9315
Contextual Info: Freescale Semiconductor Technical Data 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. The

qn04

Abstract: EP210S MC100EP210S MC100EP210SFA MC100EP210SFAR2 MARKING CODE QA1
Contextual Info: MC100EP210S 2.5V 1:5 Dual Differential LVDS Compatible Clock Driver The MC100EP210S is a low skew 1−to−5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to

Contextual Info: Freescale Semiconductor Technical Data 2.5 V and 3.3 V CMOS PLL Clock 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver Generator and Driver The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to