Q11 HBM Search Results

q11 hbm

Abstract: HEF4040B HEF4040BP HEF4040BT JESD22-A114E
Contextual Info: HEF4040B 12-stage binary ripple counter Rev. 04 — 4 March 2009 Product data sheet 1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input CP , an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The

CP/2014

Contextual Info: 74HC4040; 74HCT4040 12-stage binary ripple counter Rev. 4 — 20 March 2014 Product data sheet 1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input CP , an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to

HEF4060

Abstract: 74HC4060 74hct4060 74HC-HCT4060 DHVQFN16 SOT763-1 74HC4060D 74HC4060DB 74HC4060N 74HCT4060D
Contextual Info: 74HC4060; 74HCT4060 14-stage binary ripple counter with oscillator Rev. 03 — 14 July 2008 Product data sheet 1. General description The 74HC4060; 74HCT4060 are high-speed Si-gate CMOS device and is pin compatible with the HEF4060. The 74HC4060; 74HCT4060 are 14-stage ripple-carry counter/dividers and oscillators

74HCT4060BQ

Abstract: 74HC4060BQ
Contextual Info: 74HC4060; 74HCT4060 14-stage binary ripple counter with oscillator Rev. 03 — 14 July 2008 Product data sheet 1. General description The 74HC4060; 74HCT4060 are high-speed Si-gate CMOS device and is pin compatible with the HEF4060. The 74HC4060; 74HCT4060 are 14-stage ripple-carry counter/dividers and oscillators

Contextual Info: 74HC4040-Q100; 74HCT4040-Q100 12-stage binary ripple counter Rev. 1 — 24 March 2014 Product data sheet 1. General description The 74HC4040-Q100; 74HCT4040-Q100 is a 12-stage binary ripple counter with a clock input CP , an overriding asynchronous master reset input (MR) and twelve parallel

74HC4040

Abstract: 74HC4040 data sheet 74HC-HCT4040 mr 4040 20050914 74HC4040BQ 74HC4040D 74HC4040DB 74HC4040N 74HC4040PW
Contextual Info: 74HC4040; 74HCT4040 12-stage binary ripple counter Rev. 03 — 14 September 2005 Product data sheet 1. General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC

Contextual Info: 74HC4040; 74HCT4040 12-stage binary ripple counter Rev. 03 — 14 September 2005 Product data sheet 1. General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC

Contextual Info: HEF4060B-Q100 14-stage ripple-carry binary counter/divider and oscillator Rev. 2 — 9 September 2014 Product data sheet 1. General description The HEF4060B-Q100 is a 14-stage ripple-carry binary counter/divider and oscillator. It has three oscillator terminals RS, REXT and CEXT and ten buffered outputs (Q3 to Q9

q11 hbm

Abstract: hbm q11 aec-q100
Contextual Info: HEF4060B-Q100 14-stage ripple-carry binary counter/divider and oscillator Rev. 1 — 28 February 2013 Product data sheet 1. General description The HEF4060B-Q100 is a 14-stage ripple-carry binary counter/divider and oscillator. It has three oscillator terminals RS, REXT and CEXT and ten buffered outputs (Q3 to Q9

hbm q11

Abstract: HEF4020BT HEF4020B HEF4020BP JESD22-A114E
Contextual Info: HEF4020B 14-stage binary counter Rev. 04 — 4 December 2008 Product data sheet 1. General description The HEF4020B is a 14-stage binary counter with a clock input CP , an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to

q11 hbm

Contextual Info: HEF4040B-Q100 12-stage binary ripple counter Rev. 1 — 4 April 2013 Product data sheet 1. General description The HEF4040B-Q100 is a 12-stage binary ripple counter with a clock input CP , an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to

74HC4020

Abstract: 74HCT4020 74LV4020D 74LV4020DB 74LV4020N 74LV4020PW
Contextual Info: 74LV4020 14-stage binary ripple counter Rev. 01 — 29 November 2005 Product data sheet 1. General description The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HCT4020. The 74LV4020 is a 14-stage binary ripple counter with a clock input CP , an overriding

74HC4060

Abstract: HEF4060 74HC4060D 74HC4060DB 74HC4060N 74HCT4060 74HCT4060D 74HCT4060N JESD22-A114E HCT4060
Contextual Info: 74HC4060; 74HCT4060 14-stage binary ripple counter with oscillator Rev. 03 — 14 July 2008 Product data sheet 1. General description The 74HC4060; 74HCT4060 are high-speed Si-gate CMOS device and is pin compatible with the HEF4060. The 74HC4060; 74HCT4060 are 14-stage ripple-carry counter/dividers and oscillators

74HC-HCT4060

Abstract: 74HCT4060D 74HC4060 74HC4060D 74HC4060DB 74HC4060N 74HCT4060 74HCT4060N HEF4060 JESD22-A114E
Contextual Info: 74HC4060; 74HCT4060 14-stage binary ripple counter with oscillator Rev. 03 — 14 July 2008 Product data sheet 1. General description The 74HC4060; 74HCT4060 are high-speed Si-gate CMOS device and is pin compatible with the HEF4060. The 74HC4060; 74HCT4060 are 14-stage ripple-carry counter/dividers and oscillators

74hc4060

Abstract: 74hct4060 application notes 74HCT4060BQ 74HC4060BQ
Contextual Info: 74HC4060-Q100; 74HCT4060-Q100 14-stage binary ripple counter with oscillator Rev. 1 — 2 August 2012 Product data sheet 1. General description The 74HC4060-Q100; 74HCT4060-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky

74HC4060 oscillator application note

Abstract: 74hct4060 application notes 74HC4060 application note 74HC4060 74HC-HCT4060 RTC11 74HC4060-Q100 74HCT4060BQ 74HC4060BQ
Contextual Info: 74HC4060-Q100; 74HCT4060-Q100 14-stage binary ripple counter with oscillator Rev. 2 — 10 April 2013 Product data sheet 1. General description The 74HC4060-Q100; 74HCT4060-Q100 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky

SSTV16857

Abstract: VFBGA56 JESD22 JESD78 PCKV857 SSTL16877 TSSOP-48
Contextual Info: INTEGRATED CIRCUITS SSTV16857A 14-bit SSTL_2 registered driver with differential clock inputs Product data ICL03 — PC Motherboard ICs; Logic Products Group Philips Semiconductors 2001 Oct 04 Philips Semiconductors Product data 14-bit SSTL_2 registered driver

Contextual Info: HEF4020B-Q100 14-stage binary counter Rev. 1 — 4 June 2014 Product data sheet 1. General description The HEF4020B-Q100 is a 14-stage binary counter with a clock input CP , an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to

SSTV16857

Contextual Info: INTEGRATED CIRCUITS SSTV16857 14-bit SSTL_2 registered driver with differential clock inputs Product data Supersedes data of 2001 Dec 03 Philips Semiconductors 2002 Jun 05 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer The MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 2751 MHz and output skews less than 150 ps1, the device

SSTV16857

Abstract: sdram pcb layout 750-104 SOT480-1 A114 JESD22 JESD78 PCKV857 SSTL16877 TSSOP-48
Contextual Info: INTEGRATED CIRCUITS SSTV16857 14-bit SSTL_2 registered driver with differential clock inputs Product data Supersedes data of 2002 Jun 05 Philips Semiconductors 2002 Sep 27 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs

JESD22

Abstract: JESD78 PC3200 PCKV857 SSTVF16857 TSSOP-48 ci 2003 ci2003
Contextual Info: INTEGRATED CIRCUITS SSTVF16857 DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs Product data Philips Semiconductors 2003 Sep 19 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs

Contextual Info: ASM2I99448 May 2005 rev 0.3 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Features The ASM2I99448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of ƒ 12 LVCMOS compatible clock outputs ƒ Selectable LVCMOS and differential LVPECL

ASM2I99448

Abstract: ASM2I99448-32-ET ASM2I99448-32-LR ASM2I99448-32-LT ASM2I99448G-32-LR ASM2I99448G-32-LT MPC9448 MPC948
Contextual Info: ASM2I99448 May 2005 rev 0.3 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Features The ASM2I99448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of ƒ 12 LVCMOS compatible clock outputs ƒ Selectable LVCMOS and differential LVPECL