PS 223 16 PIN Search Results

SN65LVDM22

Abstract: SN65LVDS122 SN65LVDS122D SN65LVDS122PW SN65LVDS22 SN65LVDT122 SN65LVDT122D
Contextual Info: SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 1.5-Gbps 2 x 2 LVDS CROSSPOINT SWITCH FEATURES • DESCRIPTION Designed for Signaling Rates Up To 1.5 Gbps Total Jitter < 65 ps Pin-Compatible With SN65LVDS22 and SN65LVDM22 25 mV of Receiver Input Threshold Hysteresis

2A110

Contextual Info: SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 1.5-Gbps 2 x 2 LVDS CROSSPOINT SWITCH FEATURES • DESCRIPTION Designed for Signaling Rates Up To 1.5 Gbps Total Jitter < 65 ps Pin-Compatible With SN65LVDS22 and SN65LVDM22 25 mV of Receiver Input Threshold Hysteresis

Contextual Info: SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 1.5-Gbps 2 x 2 LVDS CROSSPOINT SWITCH FEATURES • DESCRIPTION Designed for Signaling Rates Up To 1.5 Gbps Total Jitter < 65 ps Pin-Compatible With SN65LVDS22 and SN65LVDM22 25 mV of Receiver Input Threshold Hysteresis

Contextual Info: SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 1.5-Gbps 2 x 2 LVDS CROSSPOINT SWITCH FEATURES • DESCRIPTION Designed for Signaling Rates Up To 1.5 Gbps Total Jitter < 65 ps Pin-Compatible With SN65LVDS22 and SN65LVDM22 25 mV of Receiver Input Threshold Hysteresis

Contextual Info: SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 1.5-Gbps 2 x 2 LVDS CROSSPOINT SWITCH FEATURES • DESCRIPTION Designed for Signaling Rates Up To 1.5 Gbps Total Jitter < 65 ps Pin-Compatible With SN65LVDS22 and SN65LVDM22 25 mV of Receiver Input Threshold Hysteresis

lvdt

Abstract: SN65LVDM22 SN65LVDS122 SN65LVDS122D SN65LVDS122PW SN65LVDS22 SN65LVDT122 SN65LVDT122D
Contextual Info: SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 1.5-Gbps 2 x 2 LVDS CROSSPOINT SWITCH FEATURES • DESCRIPTION Designed for Signaling Rates Up To 1.5 Gbps Total Jitter < 65 ps Pin-Compatible With SN65LVDS22 and SN65LVDM22 25 mV of Receiver Input Threshold Hysteresis

MAX3877

Abstract: MAX3877EHJ MAX3878 MAX3878EHJ
Contextual Info: 19-2062; Rev 0; 5/01 2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust Ordering Information TEMP. RANGE PIN-PACKAGE MAX3877EHJ PART -40°C to +85°C 32 TQFP-EP* MAX3877E/D* -40°C to +85°C DICE* MAX3878EHJ -40°C to +85°C 32 TQFP-EP*

MAX3644

Abstract: MAX3645 MAX3645EEE MAX3645ESE MAX3654 MC2045-2Y Pin TO PIN compatible maxim
Contextual Info: 19-3026; Rev 1; 11/04 +2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector Features ♦ Pin Compatible with the Mindspeed MC2045-2/MC2045-2Y ♦ 500µV Input Sensitivity BER = 10-12 ♦ Compatible with 4B/5B Data Coding ♦ Programmable LOS Threshold

Contextual Info: 19-2087; Rev 0; 7/01 Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC The MAX3873 is implemented in Maxim’s second-generation SiGe process and consumes only 260mW at +3.3V supply output clock disabled, low output swing . The device is available in a 4mm x 4mm 20-pin QFN

Contextual Info: 19-2087; Rev 0; 9/02 Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC The MAX3873A is implemented in Maxim’s secondgeneration SiGe process and consumes only 260mW at 3.3V supply output clock disabled, low output swing . The device is available in a 4mm x 4mm 20-pin QFN

LVDS100

Abstract: MC100EP16 SN65LVDS100 SN65LVDS100D SN65LVDS100DGK SN65LVDS101 SN65LVDT100 SN65LVDT100D SN65LVDT101
Contextual Info: SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516B − AUGUST 2002 − REVISED SEPTEMBER 2003 DIFFERENTIAL TRANSLATOR/REPEATER FEATURES D Designed for Signaling Rates 1 . 2 Gbps D Total Jitter < 65 ps D Low-Power Alternative for the MC100EP16

20CML

Contextual Info: NB4L16M 2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer/ Translator with Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL

Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES DESCRIPTION D Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives

C101

Abstract: SN65CML100 SN65CML100D SN65CML100DGK TDS6604
Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES DESCRIPTION D Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives

EP11

Abstract: LVEL11 NB6L11 NB6L11DG NB6L11DR2G
Contextual Info: NB6L11 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator The NB6L11 is an enhanced differential 1:2 clock or data fanout buffer/translator. The device has the same pinout and is functionally equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the

Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES DESCRIPTION D Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives

SN65LVDT125

Abstract: SN65LVDS125 LVDS125 SN65LVDS125DBT SN65LVDT125DBT LVDT125
Contextual Info: SN65LVDS125 SN65LVDT125 www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 LVDS 4x4 CROSSPOINT SWITCH FEATURES D Signaling Rates >1.5 Gbps per Channel D Supports Telecom/Datacom and HDTV Video Switching D Non-Blocking Architecture Allows Each Output to be Connected to Any Input

EP11

Abstract: LVEL11 NB6L11 NB6L11DG
Contextual Info: NB6L11 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator The NB6L11 is an enhanced differential 1:2 clock or data fanout buffer/translator. The device has the same pinout and is functionally equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the

SN65LVDS100

Abstract: SN65LVDS122 DS90CP22 SN65LVCP22 SN65LVCP22D SN65LVCP22PW SN65LVCP23
Contextual Info: SN65LVCP22 www.ti.com SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003 2x2 LVDS CROSSPOINT SWITCH FEATURES DESCRIPTION D High Speed >1000 Mbps Upgrade for The SN65LVCP22 is a 2x2 crosspoint switch providing greater than 1000 Mbps operation for each path. The dual

Contextual Info: SN65LVCP22 www.ti.com SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003 2x2 LVDS CROSSPOINT SWITCH FEATURES DESCRIPTION D High Speed >1000 Mbps Upgrade for The SN65LVCP22 is a 2x2 crosspoint switch providing greater than 1000 Mbps operation for each path. The dual

Contextual Info: SN65LVCP22 www.ti.com SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003 2x2 LVDS CROSSPOINT SWITCH FEATURES DESCRIPTION D High Speed >1000 Mbps Upgrade for The SN65LVCP22 is a 2x2 crosspoint switch providing greater than 1000 Mbps operation for each path. The dual

SLLD009

Abstract: SN65LVDS101D R-PDSO-G8 Package
Contextual Info: SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516A – AUGUST 2002 – REVISED OCTOBER 2002 2-Gbps DIFFERENTIAL TRANSLATOR/REPEATER FEATURES DESCRIPTION D D D D D These high-speed translators/repeaters were designed for signaling rates up to 2 Gbps to address various

SN65LVDT125

Abstract: SN65LVDS125
Contextual Info: SN65LVDS125 SN65LVDT125 www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 LVDS 4x4 CROSSPOINT SWITCH FEATURES D Signaling Rates >1.5 Gbps per Channel D Supports Telecom/Datacom and HDTV Video Switching D Non-Blocking Architecture Allows Each Output to be Connected to Any Input

DS90CP22

Abstract: SN65LVCP22 SN65LVCP22D SN65LVCP22PW SN65LVCP23 SN65LVDS100 SN65LVDS122
Contextual Info: SN65LVCP22 www.ti.com SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003 2x2 LVDS CROSSPOINT SWITCH FEATURES • • • • • • • • • • • • • High Speed >1000 Mbps Upgrade for DS90CP22 2x2 LVDS Crosspoint Switch LVPECL Crosspoint Switch Available in