PROGRAMMABLE SLEW RATE CONTROL IO Search Results

Contextual Info: SiP32419, SiP32429 Vishay Siliconix 28 V, 56 m, Load Switch with Programmable Current Limit and Slew Rate Control OPERATION DESCRIPTION FEATURES SiP32419 and SiP32429 are load switches that integrate multiple control features that simplify the design and increase

L9830

Contextual Info: L9830 MONOLITHIC LAMP DIMMER HIGH EFFICIENCY DUE TO PWM CONTROL AND POWER DMOS DRIVER LOAD CONNECTED TO GROUND CURRENT LIMITATION OVER AND UNDERVOLTAGE PROTECTION ON CHIP THERMAL PROTECTION LIMITED AND PROGRAMMABLE OUTPUT VOLTAGE SLEW RATE OPEN GROUND PROTECTION

L9830

Contextual Info: L9830 MONOLITHIC LAMP DIMMER HIGH EFFICIENCY DUE TO PWM CONTROL AND POWER DMOS DRIVER LOAD CONNECTED TO GROUND CURRENT LIMITATION OVER AND UNDERVOLTAGE PROTECTION ON CHIP THERMAL PROTECTION LIMITED AND PROGRAMMABLE OUTPUT VOLTAGE SLEW RATE OPEN GROUND PROTECTION

Contextual Info: TPS78825, TPS78833 SLVS382A – JUNE 2001 – REVISED JULY 2001 150-mA LOW-NOISE LDO WITH IN-RUSH CURRENT CONTROL FOR USB APPLICATION FEATURES D 150-mA Low-Dropout Regulator D Available in 2.5 V, 3.3 V D Programmable Slew Rate Control D Output Noise Typically 56 µVRMS

T494B475K016AS

Abstract: TPS78825 TPS78825DBVR TPS78825DBVT TPS78833 TPS78833DBVR TPS78833DBVT TPSC475K035R0600
Contextual Info: TPS78825, TPS78833 SLVS382A – JUNE 2001 – REVISED JULY 2001 150-mA LOW-NOISE LDO WITH IN-RUSH CURRENT CONTROL FOR USB APPLICATION FEATURES D 150-mA Low-Dropout Regulator D Available in 2.5 V, 3.3 V D Programmable Slew Rate Control D Output Noise Typically 56 µVRMS

usb pen drive block diagram

Contextual Info: fax id: 3549 CY2286 mmmttttmm^ _jgg. 8wwy Pentium II and K6 Clock Synthesizer/Driver with 100 MHz, AGP, 4 DIMM and USB/IO Support • Factory-EPROM programmable output drive and slew rate for optimal EMI control. Improved output drivers are designed for low EMI.

CY37256P160-125AI

Abstract: CY37256P208-125NC CY37256P160-83AI
Contextual Info: fax id: 6148 PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features — tS = 4.5 ns — tCO = 5.0 ns Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis

ultraISR CABLE

Abstract: CY37256 CY37256V CY37256P160-125UMB
Contextual Info: 7256 Back CY37256 UltraLogic 256-Macrocell ISR™ CPLD Features — tCO = 4.5 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis 5V and 3.3V I/O capability

Contextual Info: fax id: 3549 A CY2286 PRELIMINARY £ Y P R p1122 Pentium II and K6 Clock Synthesizer/Driver with 100 MHz, AGP, 4 DIMM and USB/IO Support • Factory-EPROM programmable output drive and slew rate for optimal EMI control. Improved output drivers are designed for low EMI.

Contextual Info: L6474 easySPIN – fully integrated microstepping motor driver Features • Operating voltage: 8 - 45 V ■ 7.0 A output peak current 3.0 A r.m.s. ■ Low RDSon power MOSFETS ■ Programmable power MOS slew-rate ■ Up to 1/16 microstepping ■ Current control with adaptive decay

Contextual Info: TPS65279 www.ti.com SLVSC85 – AUGUST 2013 4.5-V TO 18-V INPUT VOLTAGE, 5-A/5-A DUAL SYNCHRONOUS STEP-DOWN CONVERTER WITH CURRENT SHARING Check for Samples: TPS65279 FEATURES 1 • • • • • • • • • 4.5-V to 18-V Wide Input Voltage Range Programmable Slew Rate Control for Output

Contextual Info: DATASHEET Ultra Low Power Programmable Main Clock for VIA VX900 Chipset Recommended Application: Ultra low power main clock for VIA VX900 chipset ICS9UM709B Features/Benefits: • Supports programmable spread percentage and frequency • Uses external 14.318MHz crystal, external crystal load

EPM3256A

Abstract: 144-Pin PLCC/TQFP Package Pin-Out Diagram EPM3032A EPM3064A EPM3128A EPM3512A EPM3032A application
Contextual Info: MAX 3000A Programmable Logic Device Family December 2002, ver. 3.2 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices PLDs built on a MAX® architecture (see Table 1)

EPM7032AE

Abstract: EPM7064AE EPM7128A EPM7128AE EPM7256A JESD-71
Contextual Info: MAX 7000A October 2002, ver. 4.3 Features. • ■ ■ ■ ■ ■ ■ Altera Corporation DS-M7000A-4.3 Programmable Logic Device Data Sheet ■ f Includes MAX 7000AE High-performance 3.3-V EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

Contextual Info: MAX 7000A October 2002, ver. 4.3 Features. • ■ ■ ■ ■ ■ ■ Altera Corporation DS-M7000A-4.3 Programmable Logic Device Data Sheet ■ f Includes MAX 7000AE High-performance 3.3-V EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

Contextual Info: MAX 7000A October 2002, ver. 4.3 Features. • ■ ■ ■ ■ ■ ■ Altera Corporation DS-M7000A-4.3 Programmable Logic Device Data Sheet ■ f Includes MAX 7000AE High-performance 3.3-V EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

Contextual Info: MAX 3000A Programmable Logic Device Family June 2003, ver. 3.4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices PLDs built on a MAX® architecture (see Table 1)

QFN-32

Abstract: SMB138 QFN 5X5 QFN-64 qfn32 car battery charger SMB113 CSP-15 SMB135
Contextual Info: SMB113A/B/117 – Four-channel Programmable Power Managers for High-power Applications SMB113A/B 5A & SMB117 (10A) Combine High-performance and High-power DC/DC Regulation with Advanced Power System Control SMB113A/B SMB117 +2.7V to +6.0V or Li-Ion Features

FS12

Abstract: ICS94252
Contextual Info: ICS94252 Integrated Circuit Systems, Inc. Programmable System Clock Chip for PIII Processor Block Diagram 48MHz XTAL OSC REF0 IOAPIC SDATA SCLK PLL1 Spread Spectrum CPU DIVDER Control SDRAM DIVDER PD# PCI_STOP# CPU_STOP# MODE 0456A—12/12/02 Stop 2 13

W83194BR-903

Abstract: PSKE SEL24 W83194BG-903
Contextual Info: W83194BR-903 & W83194BG-903 STEPLESS VIA PT/PM MAIN CLOCK GENERATOR Date: 5/2/2006 Revision: 1.0 W83194BR-903/W83194BG-903 W83194BR-903 Datasheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS n.a. All of the versions before 0.50 are for internal

SEL24

Abstract: W83194BR-903
Contextual Info: W83194BR-903 WINBOND STEPLESS VIA PT/PM MAIN CLOCK GENERATOR -I- Publication Release Date: December 23, 2004 Revision 1.0 W83194BR-903 Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS n.a. All of the versions before 0.50 are for internal use.

UART TTL buffer

Abstract: HCI Transport Layers STLC2410B STW5093 M16550
Contextual Info: STLC2410B BLUETOOTH BASEBAND PRELIMINARY DATA - REV. 1.1 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Bluetooth® V1.1 specification compliant Point-to-point, point-to-multi-point up to 7 slaves and scatternet capability Asynchronous Connection-Less (ACL) link

Contextual Info: DATA SHEET DP8110G 10A DC-DC Intelligent dPOL FEATURES • Output voltage range: 0.7V–5.5V at 0 - 10A.  Programmable dynamic output voltage positioning for better load transient response  Choice of 500KHz switching for highest efficiency or 1MHz for

Contextual Info: YS12S16 DC-DC Converter Data Sheet 9.6-14 VDC Input; 0.7525-5.5 VDC Programmable @ 16A The Products: Y-Series Features Applications •     Intermediate Bus Architectures Telecommunications Data communications Distributed Power Architectures Servers, workstations