PROGRAMMABLE SLEW RATE CONTROL IO Search Results

CA3080

Abstract: programmable slew rate control IO ca3080 amp CA3060 CA3078 CA3078A CA3094 CA3Q94
Contextual Info: LiC Variable Operational Amplifiers CA3094 Programmable Power Switch/Amplifier CA3080 Programmable Op-Amp •Input control permits user to vary voltage, power bandwidth, slew rate, input and output currents •Devices can be programmed and/or signalmodulated for optimum gain, speed, band­

L9830

Contextual Info: L9830 MONOLITHIC LAMP DIMMER HIGH EFFICIENCY DUE TO PWM CONTROL AND POWER DMOS DRIVER LOAD CONNECTED TO GROUND CURRENT LIMITATION OVER AND UNDERVOLTAGE PROTECTION ON CHIP THERMAL PROTECTION LIMITED AND PROGRAMMABLE OUTPUT VOLTAGE SLEW RATE OPEN GROUND PROTECTION

T494B475K016AS

Abstract: TPS78825 TPS78825DBVR TPS78825DBVT TPS78833 TPS78833DBVR TPS78833DBVT TPSC475K035R0600
Contextual Info: TPS78825, TPS78833 SLVS382A – JUNE 2001 – REVISED JULY 2001 150-mA LOW-NOISE LDO WITH IN-RUSH CURRENT CONTROL FOR USB APPLICATION FEATURES D 150-mA Low-Dropout Regulator D Available in 2.5 V, 3.3 V D Programmable Slew Rate Control D Output Noise Typically 56 µVRMS

T494B475K016AS

Abstract: TPS78825 TPS78825DBVR TPS78825DBVT TPS78833 TPS78833DBVR TPS78833DBVT TPSC475K035R0600
Contextual Info: TPS78825, TPS78833 SLVS382A – JUNE 2001 – REVISED JULY 2001 150-mA LOW-NOISE LDO WITH IN-RUSH CURRENT CONTROL FOR USB APPLICATION FEATURES D 150-mA Low-Dropout Regulator D Available in 2.5 V, 3.3 V D Programmable Slew Rate Control D Output Noise Typically 56 µVRMS

tic 2260

Abstract: cpu 226 CY2286PVC-1
Contextual Info: fax id: 3549 Kr CY2286 PRELIMINARY Ei1i3i3 Pentium Il and K6 Clock Synthesizer/Driver with 100 MHz, AGP, 4 DIMM and USB/IO Support • Factory-EPROM programmable output drive and slew rate for optimal EMI control. Improved output drivers are designed for low EMI.

CY37256P160-125AI

Abstract: CY37256P208-125NC CY37256P160-83AI
Contextual Info: fax id: 6148 PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features — tS = 4.5 ns — tCO = 5.0 ns Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis

Contextual Info: TPS65279 www.ti.com SLVSC85A – AUGUST 2013 – REVISED DECEMBER 2013 4.5-V TO 18-V INPUT VOLTAGE, 5-A/5-A DUAL SYNCHRONOUS STEP-DOWN CONVERTER WITH CURRENT SHARING Check for Samples: TPS65279 FEATURES 1 • • 4.5-V to 18-V Wide Input Voltage Range Programmable Slew Rate Control for Output

Contextual Info: May 1995 ADVANCED INFORMATION M icro Linear ML4670 Multi-Standard Serial Transceiver G E N E R A L D E S C R IP T IO N FEA TU RES The ML4670 Multi-Standard Serial Transceiver is designed primarily for use in and with bridge, router and frame relay equipment. The device provides the serial

EPM3256A

Abstract: 144-Pin PLCC/TQFP Package Pin-Out Diagram EPM3032A EPM3064A EPM3128A EPM3512A EPM3032A application
Contextual Info: MAX 3000A Programmable Logic Device Family December 2002, ver. 3.2 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices PLDs built on a MAX® architecture (see Table 1)

EPM7032AE

Abstract: EPM7064AE EPM7128A EPM7128AE EPM7256A JESD-71
Contextual Info: MAX 7000A September 2003, ver. 4.5 Features. • ■ ■ ■ ■ ■ ■ Altera Corporation DS-M7000A-4.5 Programmable Logic Device Data Sheet ■ f Includes MAX 7000AE High-performance 3.3-V EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

EPM7032AE

Abstract: EPM7064AE EPM7128A EPM7128AE EPM7256A JESD-71
Contextual Info: MAX 7000A June 2003, ver. 4.4 Features. • ■ ■ ■ ■ ■ ■ Altera Corporation DS-M7000A-4.4 Programmable Logic Device Data Sheet ■ f Includes MAX 7000AE High-performance 3.3-V EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

DIODE PEC 812

Abstract: "Current Loop Converter" S7 PLC ladder program AD5737 ADR445 TC23 PEC 812 ad0 dac 4-20mA to SPI Converter
Contextual Info: Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity AD5757/AD5737 Preliminary Technical Data FEATURES GENERAL DESCRIPTION 16/12-Bit Resolution and Monotonicity Dynamic Power Control for Thermal Management IOUT Range: 0mA-20mA, 4mA–20mA or 0mA–24mA

QFN-32

Abstract: SMB138 QFN 5X5 QFN-64 qfn32 car battery charger SMB113 CSP-15 SMB135
Contextual Info: SMB113A/B/117 – Four-channel Programmable Power Managers for High-power Applications SMB113A/B 5A & SMB117 (10A) Combine High-performance and High-power DC/DC Regulation with Advanced Power System Control SMB113A/B SMB117 +2.7V to +6.0V or Li-Ion Features

C732B

Abstract: 337 BGA 337 BGA footprint EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE
Contextual Info: MAX 7000A Includes MAX 7000AE Programmable Logic Device Family August 2000, ver. 3.1 Data Sheet • Features. ■ ■ ■ ■ ■ ■ ■ f High-performance 3.3-V EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

Contextual Info: LSN2-T/22-D12 www.murata-ps.com Non-isolated, DOSA-SIP, 22A Selectable-Output DC/DC Converters OBSOLETE PRODUCT Last time buy: August 31, 2014. Click Here For Obsolescence Notice of February 2014. ORDERING GUIDE SUMMARY Model VOUT Range IOUT Range VIN Range

electromagnetic shielding

Contextual Info: LSN2-T/22-D12 Non-isolated, DOSA-SIP, 22A Selectable-Output DC/DC Converters ORDERING GUIDE SUMMARY Model VOUT Range IOUT Range VIN Range Ripple/Noise Efficiency 0.8-5V 0-22A 8.3-14V 35mVpk-pk 95% LSN2-T/22-D12 INPUT CHARACTERISTICS Parameter Typ. @ 25°C, full load

Contextual Info: LTC2874 Quad IO-Link Master Hot Swap Controller and PHY Description Features IO-Link Compatible COM1/COM2/COM3 8V to 30V Operation Hot Swap™ Controller Protected Supply Outputs Discrete Power MOSFETs for Ruggedness and Flexibility n Configurable 100mA (4-Port), 200mA (2-Port), or

sirf Atlas IV

Abstract: 3675f LTC3675EUFF LTC3577-1 103M capacitor Atlas SIRF 4 fb4 lt 405 810 sirf iv LPS3015-222 LTC1694
Contextual Info: LTC3675 7-Channel Configurable High Power PMIC FEATURES DESCRIPTION n The LTC 3675 is a digitally programmable high efficiency multioutput power supply plus dual string LED driver IC optimized for high power single cell Li-Ion/Polymer applications. The DC/DCs consist of four synchronous buck converters 1A/1A/500mA/500mA , one synchronous boost

EPM7032 Transition

Abstract: EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E
Contextual Info: MAX 7000 Programmable Logic Device Family September 2005, ver. 6.7 Data Sheet • Features. ■ ■ ■ ■ ■ ■ f High-performance, EEPROM-based programmable logic devices PLDs based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in

Contextual Info: LinfiAB_ mffi TECHNOLOGY |_Qw Noise S tep-D ow n S w itching R egu lator FCRTURCS D C S C R IP T IO n • ■ ■ ■ ■ ■ ■ ■ ■ The LT 1777 is a Buck step-down regulator designed for noise sensitive applications. It contains a dl/dt limiting

transistor 9614

Abstract: YNC12S20-0S1G
Contextual Info: YNC12S20 DC-DC Converter Data Sheet 9.6-14 VDC Input; 0.7525-5.5 VDC Programmable @ 20 A The Products: Y-Series Features Applications •     Intermediate Bus Architectures Telecommunications Data communications Distributed Power Architectures

epm7064 adapter

Abstract: MAX 7000 EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E
Contextual Info: MAX 7000 Programmable Logic Device Family June 2003, ver. 6.6 Features. Data Sheet • ■ ■ ■ ■ ■ ■ f High-performance, EEPROM-based programmable logic devices PLDs based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in

Contextual Info: LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters ORDERING GUIDE SUMMARY Typical Unit FEATURES Model VOUT Range IOUT Range VIN Range Ripple/Noise Efficiency LSN2-T/6-W3 0.75-3.3V 0-6A 2.4-5.5V 15mVp-p 94% LSN2-T/6-D12 0.75-5V

16 bit data bus using vhdl

Abstract: AS 108-120 MACH Programmer 1 wire verilog code 144-Pin PLCC/TQFP Package Pin-Out Diagram EPM3256A bidirectional shift register vhdl IEEE format Block diagram of 8-1 multiplexer design logic loadable counter 32 Bit loadable counter and schematics
Contextual Info: MAX 3000A Programmable Logic Device Family July 1999, ver. 1.01 Features. Data Sheet • ■ Preliminary Information ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, low-cost CMOS EEPROM-based programmable logic devices PLDs built on a Multiple Array MatriX (MAX®)