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    PROGRAMMABLE SLEW RATE CONTROL IO Search Results

    PROGRAMMABLE SLEW RATE CONTROL IO Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MR8259A/B
    Rochester Electronics LLC 8259A - Interrupt Controller, Programmable - Dual marked (5962-87518013A) PDF Buy
    27S25ADM/B
    Rochester Electronics LLC 27S25A - Programmable ROM PDF Buy
    AM27S25DM
    Rochester Electronics LLC AM27S25 - OTP ROM PDF Buy
    EP1800ILC-70
    Rochester Electronics LLC EP1800 - Classic Family EPLD PDF Buy
    EP1800GM-75/B
    Rochester Electronics LLC EP1800 - Classic Family EPLD PDF Buy

    PROGRAMMABLE SLEW RATE CONTROL IO Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CA3080

    Abstract: programmable slew rate control IO ca3080 amp CA3060 CA3078 CA3078A CA3094 CA3Q94
    Contextual Info: LiC Variable Operational Amplifiers CA3094 Programmable Power Switch/Amplifier CA3080 Programmable Op-Amp •Input control permits user to vary voltage, power bandwidth, slew rate, input and output currents •Devices can be programmed and/or signalmodulated for optimum gain, speed, band­


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    CA3094 CA3080 CA3Q94 CA3060 CA3078A CA3078 100typ. 130max programmable slew rate control IO ca3080 amp CA3060 CA3078A CA3Q94 PDF

    Contextual Info: SiP32429 Vishay Siliconix 28 V, 56 m, Load Switch with Programmable Current Limit and Slew Rate Control OPERATION DESCRIPTION FEATURES The SiP32429 is a load switch that integrates multiple control features that simplify the design and increase the reliability of


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    SiP32429 2002/95/EC. 2002/95/EC 2011/65/EU. JS709A 02-Oct-12 PDF

    L9830

    Contextual Info: L9830 MONOLITHIC LAMP DIMMER HIGH EFFICIENCY DUE TO PWM CONTROL AND POWER DMOS DRIVER LOAD CONNECTED TO GROUND CURRENT LIMITATION OVER AND UNDERVOLTAGE PROTECTION ON CHIP THERMAL PROTECTION LIMITED AND PROGRAMMABLE OUTPUT VOLTAGE SLEW RATE OPEN GROUND PROTECTION


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    L9830 L9830 PDF

    L9830

    Contextual Info: L9830 MONOLITHIC LAMP DIMMER HIGH EFFICIENCY DUE TO PWM CONTROL AND POWER DMOS DRIVER LOAD CONNECTED TO GROUND CURRENT LIMITATION OVER AND UNDERVOLTAGE PROTECTION ON CHIP THERMAL PROTECTION LIMITED AND PROGRAMMABLE OUTPUT VOLTAGE SLEW RATE OPEN GROUND PROTECTION


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    L9830 L9830 PDF

    Contextual Info: TPS78825, TPS78833 SLVS382A – JUNE 2001 – REVISED JULY 2001 150-mA LOW-NOISE LDO WITH IN-RUSH CURRENT CONTROL FOR USB APPLICATION FEATURES D 150-mA Low-Dropout Regulator D Available in 2.5 V, 3.3 V D Programmable Slew Rate Control D Output Noise Typically 56 µVRMS


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    TPS78825, TPS78833 SLVS382A 150-mA TPS78833) OT-23 TPS78825 TPS78833 OT-23) PDF

    T494B475K016AS

    Abstract: TPS78825 TPS78825DBVR TPS78825DBVT TPS78833 TPS78833DBVR TPS78833DBVT TPSC475K035R0600
    Contextual Info: TPS78825, TPS78833 SLVS382A – JUNE 2001 – REVISED JULY 2001 150-mA LOW-NOISE LDO WITH IN-RUSH CURRENT CONTROL FOR USB APPLICATION FEATURES D 150-mA Low-Dropout Regulator D Available in 2.5 V, 3.3 V D Programmable Slew Rate Control D Output Noise Typically 56 µVRMS


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    TPS78825, TPS78833 SLVS382A 150-mA TPS78833) OT-23 TPS78825 TPS78833 OT-23) T494B475K016AS TPS78825DBVR TPS78825DBVT TPS78833DBVR TPS78833DBVT TPSC475K035R0600 PDF

    T494B475K016AS

    Abstract: TPS78825 TPS78825DBVR TPS78825DBVT TPS78833 TPS78833DBVR TPS78833DBVT TPSC475K035R0600
    Contextual Info: TPS78825, TPS78833 SLVS382A – JUNE 2001 – REVISED JULY 2001 150-mA LOW-NOISE LDO WITH IN-RUSH CURRENT CONTROL FOR USB APPLICATION FEATURES D 150-mA Low-Dropout Regulator D Available in 2.5 V, 3.3 V D Programmable Slew Rate Control D Output Noise Typically 56 µVRMS


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    TPS78825, TPS78833 SLVS382A 150-mA TPS78833) OT-23 TPS78825 TPS78833 OT-23) T494B475K016AS TPS78825DBVR TPS78825DBVT TPS78833DBVR TPS78833DBVT TPSC475K035R0600 PDF

    Contextual Info: TPS78825, TPS78833 SLVS382A – JUNE 2001 – REVISED JULY 2001 150-mA LOW-NOISE LDO WITH IN-RUSH CURRENT CONTROL FOR USB APPLICATION FEATURES D 150-mA Low-Dropout Regulator D Available in 2.5 V, 3.3 V D Programmable Slew Rate Control D Output Noise Typically 56 µVRMS


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    TPS78825, TPS78833 SLVS382A 150-mA TPS78833) TPS78825 TPS78833 OT-23) TPS788xx PDF

    Contextual Info: TPS78825, TPS78833 SLVS382A – JUNE 2001 – REVISED JULY 2001 150-mA LOW-NOISE LDO WITH IN-RUSH CURRENT CONTROL FOR USB APPLICATION FEATURES D 150-mA Low-Dropout Regulator D Available in 2.5 V, 3.3 V D Programmable Slew Rate Control D Output Noise Typically 56 µVRMS


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    TPS78825, TPS78833 SLVS382A 150-mA TPS78833) TPS78825 TPS78833 OT-23) TPS788xx PDF

    usb pen drive block diagram

    Contextual Info: fax id: 3549 CY2286 mmmttttmm^ _jgg. 8wwy Pentium II and K6 Clock Synthesizer/Driver with 100 MHz, AGP, 4 DIMM and USB/IO Support • Factory-EPROM programmable output drive and slew rate for optimal EMI control. Improved output drivers are designed for low EMI.


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    CY2286 CY2286PVC-1 usb pen drive block diagram PDF

    tic 2260

    Abstract: cpu 226 CY2286PVC-1
    Contextual Info: fax id: 3549 Kr CY2286 PRELIMINARY Ei1i3i3 Pentium Il and K6 Clock Synthesizer/Driver with 100 MHz, AGP, 4 DIMM and USB/IO Support • Factory-EPROM programmable output drive and slew rate for optimal EMI control. Improved output drivers are designed for low EMI.


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    CY2286 CY2286PVC-1 tic 2260 cpu 226 CY2286PVC-1 PDF

    Contextual Info: fax id: 6150 CYPRESS PRELIMINARY Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability


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    Ultra37192 192-Macrocell IEEE1149 160-pin Ultra37256 Ultra37128 PDF

    CY37256P160-125AI

    Abstract: CY37256P208-125NC CY37256P160-83AI
    Contextual Info: fax id: 6148 PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features — tS = 4.5 ns — tCO = 5.0 ns Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis


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    Ultra37256 256-Macrocell IEEE1149 160-pin 208-pin 256-lead Ultra37192 Ultra37128 CY37256P160-125AI CY37256P208-125NC CY37256P160-83AI PDF

    ultraISR CABLE

    Abstract: CY37256 CY37256V CY37256P160-125UMB
    Contextual Info: 7256 Back CY37256 UltraLogic 256-Macrocell ISR™ CPLD Features — tCO = 4.5 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis 5V and 3.3V I/O capability


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    CY37256 256-Macrocell 160-pin 208-pin 256-lead CY37256V, CY37128/37128V, CY37192/37192V, CY37384/37384V, CY37512/37512V, ultraISR CABLE CY37256 CY37256V CY37256P160-125UMB PDF

    Contextual Info: CYPRESS PRELIMINARY Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD — tco = 4.5 ns Features Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability


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    Ultra37192 192-Macrocell IEEE1149 160-pin Ultra37192V, Ultra37128/37128V, Ultra37256/37256V, CY7C375i PDF

    O16I

    Abstract: 7256P 99L0
    Contextual Info: PREUM INAm Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability


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    Ultra37256 256-Macrocell IEEE1149 160-pin 208-pin 256-lead O16I 7256P 99L0 PDF

    Contextual Info: fax id: 3549 A CY2286 PRELIMINARY £ Y P R p1122 Pentium II and K6 Clock Synthesizer/Driver with 100 MHz, AGP, 4 DIMM and USB/IO Support • Factory-EPROM programmable output drive and slew rate for optimal EMI control. Improved output drivers are designed for low EMI.


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    CY2286 56-pin CY2286 PDF

    MP5006

    Contextual Info: MP5006 5V, 1A- 5A Programmable Current Limit Switch with Slew Rate Control and Auto Enable The Future of Analog IC Technology DESCRIPTION FEATURES The MP5006 is a protection device designed to protect circuitry on the output VOUT from transients on input (VIN). It also protects VIN from


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    MP5006 MP5006 MO-229, PDF

    CY37384

    Contextual Info: PRELIMINARY C Y37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns Product-term clocking • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os


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    Y37384 384-Macrocell 208-pin 256-lead CY37384 PDF

    CY37256P160-125AI

    Abstract: 37256P160 ieee1149.1 cypress 37-25615
    Contextual Info: fax id: 6148 1Ult ra372 56 PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features • • • • • • • • • Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis


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    ra372 Ultra37256 256-Macrocell IEEE1149 160-pin 208-pin 256-lead Ultra37000 CY37256P160-125AI 37256P160 ieee1149.1 cypress 37-25615 PDF

    CD4020

    Abstract: CD4020 timer circuit 723C CA3130 peak detector ca3130 replacement CA3085 CA3058 CA3060 CA3078 CA3078A
    Contextual Info: LiC Variable Operational Amplifiers CA3094 Programmable Power Switch/Amplifier CA3080 Programmable Op-Amp •In p u t control perm its user to vary voltage, power b a n d w id th , slew rate, input and o u tp u t currents •D evices can be program m ed and/or signalm odulated for optim um gain, speed, b an d ­


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    CA3094 CA3080 CA3Q94 CA3059 CD4020" CA3096 CA3098 CA3130 CA3097 CD4020 CD4020 timer circuit 723C CA3130 peak detector ca3130 replacement CA3085 CA3058 CA3060 CA3078 CA3078A PDF

    37-25615

    Abstract: CY37256 CY37256P160-125UMB
    Contextual Info: UltraLogic 256-Macrocell ISR™ CPLD Features — tCo = 4 -5 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 256 macrocells in sixteen logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os


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    256-Macrocell 160-pin 208-pin 256-lead CY372n 37-25615 CY37256 CY37256P160-125UMB PDF

    CY37512

    Contextual Info: UltraLogic 512-Macrocell ISR™ CPLD Features — tco = 6 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os


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    512-Macrocell 208-pin 256/352-lead CY37512V, CY37512 PDF

    Contextual Info: TPS65279 www.ti.com SLVSC85A – AUGUST 2013 – REVISED DECEMBER 2013 4.5-V TO 18-V INPUT VOLTAGE, 5-A/5-A DUAL SYNCHRONOUS STEP-DOWN CONVERTER WITH CURRENT SHARING Check for Samples: TPS65279 FEATURES 1 • • 4.5-V to 18-V Wide Input Voltage Range Programmable Slew Rate Control for Output


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    TPS65279 SLVSC85A PDF