POS-PHY UTOPIA Search Results

PMC-971147

Abstract: POS-PHY ATM format
Contextual Info: COMPATIBILITY SPECIFICATION PMC-Sierra, Inc. POS-PHY Level 2 PMC-971147, ISSUE 5 SATURN-COMPATIBLE INTERFACE FOR POS PHY DEVICES POS-PHY™ SATURN COMPATIBLE

PMC-1980495

Abstract: STM-16 STS-48 TSX 017
Contextual Info: PMC-Sierra, Inc. COMPATIBILITY SPECIFICATION POS-PHY Level 3 PMC-1980495, ISSUE 4 SATURN-COMPATIBLE INTERFACE FOR POS PHY DEVICES POS-PHY™ Level 3 SATURN COMPATIBLE

implement motorola bts

Abstract: NPIS64
Contextual Info: Fact Sheet Freescale Semiconductor, Inc. M-2 UTOPIA / POS-PHY ADAPTER REFERENCE DESIGN Freescale Semiconductor, Inc. PRELIMINARY FEATURES • Adapts the C-3e and C-5e Network Processor interfaces to support single-PHY and multiPHY Utopia and POS-PHY L2, 16 bit interfaces

CX29704

Abstract: F155 GR-253 GR-253-CORE
Contextual Info: A CONEXANT BUSINESS OptiPHY™ F155 Quad OC-3/STM-1 ATM/POS PHY CX29704 Four-Channel, 155 Mbps ATM/POS PHY with Clock and Data Recovery, UTOPIA Level 2 and POS Level 2 The CX29704 is an integrated circuit that implements four-channel ATM/Packet over SONET/SDH POS

scrambling

Abstract: CX29704 F155 GR-253 GR-253-CORE mindspeed JTAG ATM circuit diagram
Contextual Info: OptiPHY F155 Quad OC-3/STM-1 ATM/POS PHY CX29704/2/1 Four-Channel CX29704, two-channel CX29702, one-channel CX29701 155Mbps ATM/POS PHY with Clock and Data Recovery The CX2970x is an integrated circuit that implements four-channel ATM/Packet over SONET/SDH POS

POS-PHY ATM format

Contextual Info: Sertopia Device UTOPIA Serializer TXC-05860 DESCRIPTION • In-band UTOPIA and POS-PHY Level 2 operating modes for cell and packet traffic • UTOPIA Level 2, and POS-PHY operating modes for cell and packet traffic • One UTOPIA port up to 800 Mbit/s

8B10B

Abstract: 8B10B in serial communication
Contextual Info: µPD98441, µPD98442 eTR Utopia/POS-PHY to LVDS Interface Product Letter Description Express Transmitter Receiver for short: eTR is a powerful transceiver chip family designed to deliver reliable full-duplex high-speed point-to-point UTOPIA/POS-PHY data transfer over a serial LVDS link, either via the

STS-192

Abstract: STS-48 VSC9112
Contextual Info: SONET/SDH IP/ATM Framer and Mapper Framers and Mappers VSC9112 Product Brief Features: System / Packet Interface • 32-bit Industry Compliant POS-PHY-3, Single-PHY Packet Interface • 32-bit Industry Compliant UTOPIA-3, Single-PHY Cell Interface Physical Layer Channelization

DMX chip

Abstract: DMX single chip controller STS-192 STS-48 VSC9142
Contextual Info: SONET/SDH IP/ATM Framer and Mapper VSC9142 Framers and Mappers Product Brief Features: System / Packet Interface • 32-bit Industry Compliant POS-PHY-3, Single-PHY Packet Interface • 32-bit Industry Compliant UTOPIA-3, Single-PHY Cell Interface Physical Layer Channelization

LG1627BXC

Abstract: TADM042G5 TDAT042G5 TRCV012G5 TTRN012G5 IXF1002 IXF440 transmit data through ethernet to fpga by vhdl
Contextual Info: Product Brief June 2001 Gigabit Ethernet/Fast Ethernet POS-PHY Bridge Overview The gigabit Ethernet GbE /fast Ethernet POS-PHY bridge enables system solutions to be created for two different applications. The first application involves transporting GbE frames or 10 Mbits/s/100 Mbits/s

fifo vhdl

Abstract: POS-PHY pmc OC48 PM5351 PM7325 ep1m20 vhdl code for phy interface
Contextual Info: POS-PHY Level 2 & 3 Compiler MegaCore Functions April 2001 User Guide v0.5.0 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-POS-PHY_COMP-0.5.0 POS-PHY Level 2 & 3 Compiler MegaCore Functions User Guide Altera, ACEX, APEX, APEX 20K, MegaCore, MegaWizard, Mercury, OpenCore, Quartus and Quartus II are trademarks and/or

GR-253-CORE

Abstract: PM5358 PM5379 PM5382 "network interface cards"
Contextual Info: PM5379 S/UNI 4x155 Release 4-Channel OC-3c ATM and POS Physical Layer Device FEATURES • Provides UTOPIA Level 3 compatible 32-bit wide System Interface clocked up to 104 MHz with parity support for ATM applications. • Provides SATURN POS-PHY Level 3 32-bit System Interface

TSX 47 software

Abstract: "network interface cards"
Contextual Info: PM5379 S/UNI 4x155 Release 4-Channel OC-3c ATM and POS Physical Layer Device FEATURES • Provides UTOPIA Level 3 compatible 32-bit wide System Interface clocked up to 104 MHz with parity support for ATM applications. • Provides SATURN POS-PHY Level 3 32-bit System Interface

Gigabit Ethernet PHY

Abstract: PM3386 PM5358 PM5381 PM5382 PM7390
Contextual Info: PM3386 S/UNI -2xGE Dual Gigabit Ethernet Controller PMC-1991223 R4 • Standard OC-48 bandwidth Packet/Cell interface. • Compatible with PMC-Sierra devices supporting POS-PHY Level 3, including: • PM5381 S/UNI®-2488 ATM and POS physical layer device.

cd 1619

Contextual Info: PM5357 S/UNI-622-POS PMC-Sierra,Inc. 622 Mbit/s ATM and Packet Over SONET Physical Layer Device FEATURES GENERAL ATM and Packet over SONET/SDH POS OC-12c (622 Mbit/s) PHY Provides on-chip clock and data recovery and clock synthesis Exceeds Bellcore-GR-253 jitter

XAPP623

Contextual Info: POS-PHY Level-4 Core v5.0 DS209 August 7, 2002 Product Specification LogiCORE Facts Features • Fully compliant with OIF-SPI4-02.0 System Packet Interface Level-4 SPI-4 Phase 2 standard • Supports POS, ATM, and Ethernet 10 Gbps applications • Delivered through CORE Generator providing easy

GR-253-CORE

Abstract: PM5358 PM5382
Contextual Info: PM5380 S/UNI 8x155 Released 8-Channel OC-3c ATM and POS Physical Layer Device FEATURES DEVICE INTERNETWORKING Other PMC-Sierra devices that implement the POS-PHY Level 3 interface include: • S/UNI 12xJET • S/UNI 4x622 • S/UNI 2488 • S/UNI 2xGE • S/UNI MACH48

Contextual Info: PHAST -12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412 DATA SHEET PRODUCT PREVIEW Line/Path Ring Ports LINE SIDE APPLICATIONS • SDH/SONET add/drop and terminal multiplexers • Linear MS/Line protection

g803

Contextual Info: PHAST-12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412B DATA SHEET PRELIMINARY TXC-06412B-MB, Ed. 3 December 2006 FEATURES • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and

mpa08

Abstract: 178 09T AU-AIS PMC-971147 GR-253-CORE MPC8260 MPC860 TXC-06412 DSLAM structure MPD13
Contextual Info: PHAST -12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412 DATA SHEET PRODUCT PREVIEW Line/Path Ring Ports LINE SIDE APPLICATIONS • SDH/SONET add/drop and terminal multiplexers • Linear MS/Line protection

Contextual Info: PHAST -12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412 DATA SHEET PRODUCT PREVIEW Line/Path Ring Ports LINE SIDE APPLICATIONS • SDH/SONET add/drop and terminal multiplexers • Linear MS/Line protection

Contextual Info: PHAST-12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412B DATA SHEET PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 FEATURES • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and

PHAST-12P

Abstract: 1211 G integrated circuit
Contextual Info: PHAST -12P Device STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06412 DATA SHEET PRODUCT PREVIEW Line/Path Ring Ports LINE SIDE APPLICATIONS • SDH/SONET add/drop and terminal multiplexers • Linear MS/Line protection

ATM126

Contextual Info: PHAST-6P Device Dual STM-1/OC-3 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface TXC-06406B DATA SHEET PRODUCT PREVIEW TXC-06406B-MB, Ed. 1 May 2005 FEATURES APPLICATIONS • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery