PORT INTERCONNECT Search Results

ECP88

Contextual Info: PARALLEL PORT The FDC37C669 incorporates an IBM XT/AT compatible parallel port. The FDC37C669 supports the optional PS/2 type bi­ directional parallel port SPP , the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the

AL010

Abstract: AR11 AR12 CY7C132 CY7C142 DR31 "Single-Port RAM"
Contextual Info: Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in

dual port ram

Abstract: AR11 AR12 CY7C132 CY7C142 DR31
Contextual Info: Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in

BC634

Abstract: AA012 DSP56800 bc645 BC699 bc657
Contextual Info: SECTION 12 JTAG PORT DSP56L811 User’s Manual 12-1 JTAG Port 12.1 12.2 12.3 12.4 12.5 12-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 JTAG PORT ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 12-4 JTAG/ONCE PORT PINOUT. . . . . . . . . . . . . . . . . . . . . . . . 12-5

CYPRESS CROSS REFERENCE dual port sram

Abstract: 1024 byte dual port memory "8-Bit Microprocessors" CY7C132 dual port sram dual port SRAM PLCC dual-port RAM AR11 AR12 CY7C142
Contextual Info: fax id: 5300 Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in

Contextual Info: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Datasheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

Contextual Info: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24BG2 Datasheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

Contextual Info: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24AG2 Datasheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

XRS10L240

Abstract: sor1 redundant transmission signal path designer
Contextual Info: PRELIMINARY XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR MARCH 2006 REV. P1.0.1 INTRODUCTION The XRS10L240 device provides the combined advantages of the Serial ATA II Port Selector and Port Multiplier implementations for Serial ATA II systems

Contextual Info: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24AG2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

89H16NT16G2

Abstract: 89HPES16NT16G2
Contextual Info: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

PM3370

Abstract: PM3380 PM3390
Contextual Info: /D\HUDQG*LJDELW WKHUQHW6ZLWFKLQJ 6ROXWLRQV EXACT Port Controller (PM3380, PM3370 EXACT Port Controller (PM3380, PM3370) EXACT Port Controller (PM3380, PM3370) EXACT Port Controller (PM3380, PM3370) Optional EXACT Switch Matrix Controller (PM3390)

port expander 32-bit i2c

Abstract: 89HPES32NT24BG2 89H32NT24BG2
Contextual Info: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24BG2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

PES32NT24AG2

Abstract: 89H32NT24A 89H32NT24 89H32NT24AG2 89HPES32NT24AG2
Contextual Info: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24AG2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

89HPES32NT24BG2

Abstract: 89H32NT 89H32NT24 PES32NT24BG2 89H32NT24BG2
Contextual Info: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24BG2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

89HPES16NT16G2

Abstract: 89hpes16nt16g2 port interconnect 89H16NT16 89H16NT16G2
Contextual Info: 16-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES16NT16G2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

Contextual Info: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24BG2 Data Sheet ® Device Overview • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

M1012L

Abstract: 7 segmen CASE DIODE A5L
Contextual Info: QS7025A PRELIMINARY Q High-Speed CMOS 8K x 16 Asynchronous Dual-Port RAM FEATURES QS7025A DESCRIPTION High-speed asynchronous dual-port architecture Access times from either port, 20/25/35/55 ns Industry standard pin-out Independent port access and control

Signal Path Designer

Contextual Info: jy&cm RF Hybrid Devices Overview its difference port. Opposite ports of the hybrid are isolated. Figure 1 is a functional diagram which will be used in this article to represent the 180° hybrid. Port B can be considered the sum port with port A the difference port. Ports A and B and ports

7 segmen

Abstract: 11DDDD
Contextual Info: QS7025A PRELIMINARY High-Speed CMOS 8K x 16 Asynchronous Dual-Port RAM Q FEATURES QS7025A DESCRIPTION High-speed asynchronous dual-port architecture Access times from either port, 20/25/35/55 ns Industry standard pin-out Independent port access and control

simple switch block diagram

Abstract: PM3370 PM3380 PM3390
Contextual Info: PM3380 Preliminary Information PM3380 Gigabit Switch Port Controller FEATURES VLAN EXACT INTERWORKING • Monolithic intelligent Gigabit Ethernet Switch Port Controller. • Allows up to 32 Port or MAC based VLANs. • Interworks with the PM3370 Octal 10/100 Switch Port Controller.

Contextual Info: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24AG2 Data Sheet ® Devic e Ove r vie w • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions

XRS10L240

Abstract: MDIO 000D MDIO clause 45 specification
Contextual Info: PRELIMINARY & CONFIDENTIAL EXTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR JUNE 2006 1.0 REV. P1.0.2 INTRODUCTION The XRS10L240 provides the combined advantages of the Serial ATA II Port Selector and Port Multiplier implementations for Serial ATA II systems at 3.0

Contextual Info: 32-Lane 24-Port PCIe Gen2 System Interconnect Switch 89HPES32NT24BG2 Data Sheet ® Devic e Ove r vie w • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions