PO11 T Search Results

PO22

Abstract: PO-99 PO44 ATL35 PO33 PO55 CMOS GATE ARRAY AO40
Contextual Info: PO11 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: Tristate output buffer, 2mA drive Truth Table: AO E0 PO11 E0 A0 E0 | P -X | Z 1 | 0 1 1 | 1 P E0 pchn2pad_x1 I1 AO AO gateP gateN outputDRVS1 I3 P I2 nchn2pad_x1 / $Revision: 1.35 $

1025460

Abstract: 7805 UA1044 UA1068 UA1084 UA1100 UA1120 UA1132 UA1144 UA1160
Contextual Info: Features • • • • • • • • • • • • • • • • • High performance ULC family suitable for large-sized CPLDs and FPGAs Conversion to 1,000,000 gates Pin counts to over 976 pins Any pin–out matched due to limited number of dedicated pads

52887

Abstract: UA2044 UA2084 UA2100 UA2120 UA2132 UA2144 UA2160 UA2184 UA2208
Contextual Info: Features • • • • • • • • • • • • • • • • • • • High performance ULC family suitable for large-sized CPLDs and FPGAs Conversions to over 2,000,000 FPGA gates Pin counts to over 976 pins Any pin–out matched due to limited number of dedicated pads

UA1044

Abstract: UA1068 UA1084 UA1100 UA1120 UA1132 UA1144 UA1160 UA1184 UA1208
Contextual Info: UA1 Series 0.35 µm ULC Series Description The UA1 series of ULCs is well suited for conversion large sized CPLDs and FPGAs. Devices are implemented in high–performance CMOS technology with 0.35–µ m drawn channel lengths, and are capable of supporting

USD210

Abstract: USD228 USD256 USD312 USD384 USD432 USD492 USD594 USD700
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • High-performance ULC Family Suitable for Large-sized CPLDs and FPGAs From 46K Gates up to 780K Gates Supported From 18 Kbit to 390 Kbit DPRAM Compatible with Xilinx or Altera

MCGA-349

Abstract: MQFPF196 988000
Contextual Info: Pages 1 to 29 INTEGRATED CIRCUITS, SILICON MONOLITHIC, CMOS, GATE ARRAY/EMBEDDED ARRAY BASED ON TYPE MH1RT ESCC Detail Specification No. 9202/076 Issue 2 July 2007 Document Custodian: European Space Agency - see https://escies.org ESCC Detail Specification No. 9202/076

MH1099

Abstract: MH1242 PO11V5 4138G
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

Contextual Info: Pin Arrangement 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 ) FP-144H Top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

A101

Abstract: A201 MH1099E MH1156E MH1242E MH1332E AMI 1108
Contextual Info: Features • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

A101

Abstract: A201 MH1099E MH1156E MH1242E MH1332E atmel 838 atmel edac dsp radiation hard
Contextual Info: Features • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

atmel 228

Abstract: USD160 USD208 USD228 USD256 USD312 USD352 USD432 USD484 USD700
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • High performance ULC family suitable for large-sized CPLDs and FPGAs From 46K gates up to 780K gates supported From 18 Kbit to 390 Kbit DPRAM 100% compatible with Xilinx or Altera

ATMEL 634

Abstract: MH1099 MH1242 PO11V5 dual lvds vhdl
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

Contextual Info: Features • • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

Contextual Info: REVISIONS LTR DATE YR-MO-DA APPROVED A Add case outline Y. - phn DESCRIPTION 08-11-04 Thomas M. Hess B Removed “ground lid” note for case outline X in section 1.2.4 and in figure 1. phn 09-01-14 Charles F. Saffle C Add case outline Z. - phn 10-07-12

VSSP83

Abstract: PD71
Contextual Info: Pin Description 1.3.1 Pin Arrangement ) PLLVss PF6/ PF5/ PF4/ PF3/ PF2/ / PF1/ / PF0/ P65/TMO1/ P64/TMO0/ P63/TMCI1/ P62/TMCI0/ PD0/D8 PD1/D9 PD2 / D10 PD3 / D11 Vss PD4 / D12 PD5 / D13 PD6 / D14 PLLVcc PF7/φ Vss XTAL EXTAL Vcc FP-144G Top view) 72 71

A101

Abstract: A201 MH1099E MH1156E MH1242E MH1332E HEX TO DECIMAL ATMEL 220 dsp radiation hard
Contextual Info: Features • • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

atmel 216

Abstract: ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state ATL35 atmel 334 20PCI atmel h 952
Contextual Info: Features • High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 nominal • Up to 2.7 Million Used Gates and 976 Pins • System Level Integration Technology – Cores: ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores

mcga

Abstract: MCGA-349 MCGA472 MQFPF196 MCGA349 bi 370 transistor MQFPT352 988000 E1 3007
Contextual Info: Pages 1 to 29 INTEGRATED CIRCUITS, SILICON MONOLITHIC, CMOS, GATE ARRAY/EMBEDDED ARRAY BASED ON TYPE MH1RT ESCC Detail Specification No. 9202/076 Issue 3 March 2010 Document Custodian: European Space Agency - see https://escies.org ESCC Detail Specification No. 9202/076

PO88

Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5
Contextual Info: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:

qml-38535

Abstract: smd code MH1
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Add case outline Y. - phn 08-11-04 Thomas M. Hess B Removed “ground lid” note for case outline X in section 1.2.4 and in figure 1. phn 09-01-14 Charles F. Saffle REV SHEET REV SHEET REV A A A SHEET 15

H8S-2398

Abstract: h8s 2352 TFP-120 H8S-2357 FP120
Contextual Info: 1.3 Pin Description 1.3.1 Pin Arrangement P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 /TEND1 P62 /DREQ1 P61 /TEND0/CS5 90 89 88 87 86

atmel 838

Abstract: atmel 906 ATMEL 712 atmel 532 ATMEL 706 atmel 751 BGA 168 atmel 635 atmel 344 verilog code for 32 bit risc processor
Contextual Info: Features • High-speed - 100 ps Gate Delay - 2-input NAND, FO = 2 nominal • Up to 6.9 Million Used Gates and 976 Pins • System Level Integration Technology – Cores: ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores

73D12

Abstract: qfp128 IO769 120 QFP 128p30
Contextual Info: 1.3 Pin Description 1.3.1 Pin Arrangement PLLVCC PF6/ PF5/ PF4/ PF3/ PF2/ / PF1/ / PF0/ / PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 VSS P81/TxD3 P83/RxD3 VCC VCC EXTAL XTAL VSS PF7/φ PLLVSS 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76