PLL 02 A Search Results

pll 02 a

Abstract: PLL-02 PLL02 PLL-01 C7B12
Contextual Info: The Analog Mixed Signal Company PLL ID: 052 PLL-01 Name Description This phase locked loop PLL is designed for low voltage applications. For this circuit, the C7B12 process technology is used. This topology is more sophisticated than that of the PLL-02. In this PLL, a linear VCO in combination with a low

HC49

Abstract: ICS813252CKI-02 ICS813252I-02 ICS814252CKI-02 ICS814252I-02 MO-220 ics452
Contextual Info: PRELIMINARY ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER GENERAL DESCRIPTION FEATURES The ICS814252I-02 is a member of the ICS HiperClockS™ family of high performance clock HiPerClockS™ solutions from IDT. The ICS814252I-02 is a PLL

Contextual Info: Micro Networks M2004-02 An Integrated Circuit Systems Company Preliminary Specifications M2004-02 Frequency Synthesizer DESCRIPTION The M2004-02 integrates a high performance Phase Locked Loop PLL with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency

sstl lvttl Translator

Contextual Info: Micro Networks M2004-02 An Integrated Circuit Systems Company Preliminary Specifications M2004-02 Frequency Synthesizer DESCRIPTION The M2004-02 integrates a high performance Phase Locked Loop PLL with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency

TDA1591

Abstract: CSB456F11 DIP20 SO20 TDA1591T TDA1596 pilot canceller
Contextual Info: INTEGRATED CIRCUITS DATA SHEET TDA1591 PLL stereo decoder and noise blanker Product specification Supersedes data of March 1992 File under Integrated Circuits, IC01 1996 Sep 02 Philips Semiconductors Product specification PLL stereo decoder and noise blanker

664G02LF

Abstract: ICS661 ICS664-02 LP2985 ICS660 664G-02LFT hd-sdi pcb layout
Contextual Info: DATASHEET ICS664-02 PECL DIGITAL VIDEO CLOCK SOURCE Description Features The ICS664-02 provides clock generation and conversion for clock rates commonly needed in HDTV digital video equipment. The ICS664-02 uses the latest Phase-Locked Loop PLL technology to provide excellent phase noise

pll 02 a

Abstract: PLL-02 470nF C7B12
Contextual Info: The Analog Mixed Signal Company PLL ID: 053 PLL-02 Name Description This phase locked loop PLL is designed for low voltage applications. For this circuit, the C7B12 process is used. An advantage of this topology is it's great simplicity. If you want to change the output frequency, change the clock divider

Contextual Info: MC33596 Rev. 5, 02/2010 Freescale Semiconductor Data Sheet MC33596 PLL Tuned UHF Receiver for Data Transfer Applications Overview The MC33596 is a highly integrated receiver designed for low-voltage applications. It includes a programmable PLL for multi-channel applications,

CN58xx

Abstract: ICS8430S10BYI-02 ICS8430S10I-02 MS-026
Contextual Info: Clock Generator for Cavium Processors ICS8430S10I-02 DATA SHEET General Description Features The ICS8430S10I-02 is a PLL-based clock generator specifically designed for Cavium Networks SoC HiPerClockS processors. This high performance device is optimized

Contextual Info: MC33696 Rev. 12, 02/2010 Freescale Semiconductor Data Sheet MC33696 PLL Tuned UHF Transceiver for Data Transfer Applications Overview The MC33696 is a highly integrated transceiver designed for low-voltage applications. It includes a programmable PLL for multi-channel applications,

SC409

Abstract: SC425 s3012 sc419 S3310 SC422 clock chips
Contextual Info: ‘I IMISC4XX SYSTEM CLOCK CHIPS CMOS LSI PLL FREQUENCY SYNTHESIZER January 1993 DESCRIPTION FEA TURES • Multiple PLL Clock Generators Provide All Essential Clock Signals for Computer C P U Boards. ■ Supports 8 02 8 6 , 80386 , and 8 0486 Based Designs.

MO-220

Abstract: HC49 ICS13252I-02 ICS813252CKI-02 ICS813252I-02 ICS3252CI02 32-VFQFN
Contextual Info: Jitter Attenuator & FemtoClock Multiplier ICS813252I-02 DATA SHEET GENERAL DESCRIPTION FEATURES The ICS813252I-02 is a PLL based synchronous ICS multiplier that is optimized for PDH or SONET to HiPerClockS™ Ethernet clock jitter attenuation and frequency

CN58XX

Contextual Info: Clock Generator for Cavium Processors ICS8430S10I-02 DATA SHEET General Description Features The ICS8430S10I-02 is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core

Contextual Info: ICS810252DI-02 VCXO Jitter Attenuator & FemtoClock Multiplier DATA SHEET General Description Features The ICS810252DI-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency

CLK180

Abstract: ICS672-01 ICS672-02 ICS672M-01 ICS672M-01T
Contextual Info: ICS672-01/02 QuadraClock Quadrature Delay Buffer Description Features The ICS672-01 and ICS672-02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on ICS’ proprietary low jitter Phase Locked Loop PLL

181M02LF

Abstract: ICS181-02 W181-02
Contextual Info: DATASHEET ICS181-02 LOW EMI CLOCK GENERATOR Description Features The ICS181-02 generates a low EMI output clock from a clock or crystal input. The device uses IDT’s proprietary mix of analog and digital Phase-Locked Loop PLL technology to spread the frequency

Contextual Info: ICS810252DI-02 VCXO Jitter Attenuator & FemtoClock Multiplier NRND DATA SHEET General Description Features The ICS810252DI-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency

ICS580-01

Abstract: ICS581-01 ICS58102 ICS581-02 ICS581G-01 ICS581G-01I ICS581G-01T ICS581G-02 ICS581G-02T
Contextual Info: ICS581-01, -02 Zero-Delay Glitch-Free Clock Multiplexer Description Features The ICS581-01 and ICS581-02 are glitch free, Phase Locked Loop PLL based clock multiplexers (mux) with zero delay from input to output. They each have 4 low skew outputs which can be

PL671-02

Contextual Info: PL671-02 PicoEMI T M Spread Spectrum Clock Generator FEATURES PIN CONFIGURATION PDB^, CLK1 1 GND 2 FIN 3 PL671-02 • Advanced programmable PLL with Spread Spectrum  Reference Clock input o 1MHz to 200MHz  Output Frequency o <200MHz  Two programmable I/O pins

tc9137p

Abstract: TC9137BP TD6301AP E310 fet tc9137 td6104 td6301 td6301ap toshiba E310D TC9137BF
Contextual Info: 't O S H ^ T e LECTRONIC „ _ 02 D e | ciQc17E47~0017ciDci o | -. — • ; T-5o"n C-MOS LSI FOR STATIC TYPE DIGITAL TUNING SYSTEM. Unit in mm TC9137BP/BF are LSI for PLL synthesizer type digital tuning system with PLL circuit and control « circuit centralized'into one chip.

ICS507-01

Abstract: ICS507-02 ICS507M-01 ICS507M-01I ICS507M-01T MAN09
Contextual Info: ICS507-01/02 PECL Clock Synthesizer Description Features The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz or other high speed differential PECL clock output from a low frequency crystal input. Using Phase-LockedLoop (PLL) techniques, the devices use a standard

Contextual Info: ICS507-01/02 PECL Clock Synthesizer Description Features The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz or other high speed differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard

CLK180

Abstract: ICS672-01 ICS672-02 672M-02LF
Contextual Info: DATASHEET ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER Description Features The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT’s proprietary low jitter Phase-Locked Loop PLL techniques, each device provides five low-skew

CLK180

Abstract: ICS672-01 ICS672-02
Contextual Info: DATASHEET ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER Description Features The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT’s proprietary low jitter Phase-Locked Loop PLL techniques, each device provides five low-skew