PLL 02 A Search Results

pll 02 a

Abstract: PLL-02 PLL02 PLL-01 C7B12
Contextual Info: The Analog Mixed Signal Company PLL ID: 052 PLL-01 Name Description This phase locked loop PLL is designed for low voltage applications. For this circuit, the C7B12 process technology is used. This topology is more sophisticated than that of the PLL-02. In this PLL, a linear VCO in combination with a low

HC49

Abstract: ICS813252CKI-02 ICS813252I-02 ICS814252CKI-02 ICS814252I-02 MO-220 ics452
Contextual Info: PRELIMINARY ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER GENERAL DESCRIPTION FEATURES The ICS814252I-02 is a member of the ICS HiperClockS™ family of high performance clock HiPerClockS™ solutions from IDT. The ICS814252I-02 is a PLL

Contextual Info: Micro Networks M2004-02 An Integrated Circuit Systems Company Preliminary Specifications M2004-02 Frequency Synthesizer DESCRIPTION The M2004-02 integrates a high performance Phase Locked Loop PLL with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency

Contextual Info: Micro Networks M2005-02 An Integrated Circuit Systems Company Preliminary Specifications M2005-02 Frequency Translator DESCRIPTION The M2005-02 integrates a high performance Phase Locked Loop PLL with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency

M2004-02

Contextual Info: Micro Networks M2004-02 An Integrated Circuit Systems Company Preliminary Specifications M2004-02 Frequency Synthesizer DESCRIPTION The M2004-02 integrates a high performance Phase Locked Loop PLL with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency

TDA1591

Abstract: CSB456F11 DIP20 SO20 TDA1591T TDA1596 pilot canceller
Contextual Info: INTEGRATED CIRCUITS DATA SHEET TDA1591 PLL stereo decoder and noise blanker Product specification Supersedes data of March 1992 File under Integrated Circuits, IC01 1996 Sep 02 Philips Semiconductors Product specification PLL stereo decoder and noise blanker

664G02LF

Abstract: ICS661 ICS664-02 LP2985 ICS660 664G-02LFT hd-sdi pcb layout
Contextual Info: DATASHEET ICS664-02 PECL DIGITAL VIDEO CLOCK SOURCE Description Features The ICS664-02 provides clock generation and conversion for clock rates commonly needed in HDTV digital video equipment. The ICS664-02 uses the latest Phase-Locked Loop PLL technology to provide excellent phase noise

PL611S-03

Abstract: XTAL 50MHZ
Contextual Info: Preliminary PL611s-02/03 1.8V-3.3V PicoPLL TM Programmable Quick Turn Clock T M FEATURES PAD CONFIGURATION & DIE SPEC. 0.85mm (850µmx750µm) Advanced One Time Programmable PLL design. XIN XOUT Programmable PLL or Direct Oscillation operation. OE, FSEL,

Contextual Info: MC33596 Rev. 5, 02/2010 Freescale Semiconductor Data Sheet MC33596 PLL Tuned UHF Receiver for Data Transfer Applications Overview The MC33596 is a highly integrated receiver designed for low-voltage applications. It includes a programmable PLL for multi-channel applications,

CN58xx

Abstract: ICS8430S10BYI-02 ICS8430S10I-02 MS-026
Contextual Info: Clock Generator for Cavium Processors ICS8430S10I-02 DATA SHEET General Description Features The ICS8430S10I-02 is a PLL-based clock generator specifically designed for Cavium Networks SoC HiPerClockS processors. This high performance device is optimized

Contextual Info: MC33696 Rev. 12, 02/2010 Freescale Semiconductor Data Sheet MC33696 PLL Tuned UHF Transceiver for Data Transfer Applications Overview The MC33696 is a highly integrated transceiver designed for low-voltage applications. It includes a programmable PLL for multi-channel applications,

dr1 433.92

Abstract: 433.92 MHz Edd 44 AEC-Q100-002 LQFP32 MC33696 QFN32 C4138 NX5032GA has polarity dme common base amplifier circuit designing
Contextual Info: Freescale Semiconductor Data Sheet MC33696 Rev. 12, 02/2010 MC33696 PLL Tuned UHF Transceiver for Data Transfer Applications Overview The MC33696 is a highly integrated transceiver designed for low-voltage applications. It includes a programmable PLL for multi-channel applications,

fm transmitter 5km

Abstract: SIEMENS saw filter 44 MHz M3951M std924 V18DC TDA9819 SIF-232
Contextual Info: INTEGRATED CIRCUITS DATA SHEET TDA9819 Multistandard vision and sound-IF PLL with DVB-IF processing Product specification Supersedes data of 1996 Aug 02 File under Integrated Circuits, IC02 1998 Jul 14 Philips Semiconductors Product specification Multistandard vision and sound-IF PLL with

GR-1244

Abstract: MAN05 MK2049-02 MK2049-34 TR62411 ECHU1C104JB5 ETS300
Contextual Info: MK2049-02/03 Communications Clock PLLs Description Features The MK2049-02 and MK2049-03 are PhaseLocked Loop PLL based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other

Contextual Info: ICS810252DI-02 VCXO Jitter Attenuator & FemtoClock Multiplier DATA SHEET General Description Features The ICS810252DI-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency

MK1714-02RITR

Abstract: MK1714-02 MK1714-02R MK1714-02RI
Contextual Info: DATASHEET MK1714-02 SPREAD SPECTRUM MULTIPLIER CLOCK Description Features The MK1714-02 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread designed to generate high frequency clocks with low EMI. Using analog/digital Phase Locked Loop PLL

MK1714-02

Abstract: MK1714-02R MK1714-02RI MK1714-02RITR MK1714-02RTR frequency multiplier X3
Contextual Info: MK1714-02 Spread Spectrum Multiplier Clock Description Features The MK1714-02 is a low cost, high performance clock synthesizer with selectable multipliers and spread amounts percentages , designed to generate high frequency clocks with low EMI. Using analog/digital Phase-Locked Loop (PLL)

Contextual Info: ICS810252DI-02 VCXO Jitter Attenuator & FemtoClock Multiplier NRND DATA SHEET General Description Features The ICS810252DI-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency

ICS580-01

Abstract: ICS581-01 ICS58102 ICS581-02 ICS581G-01 ICS581G-01I ICS581G-01T ICS581G-02 ICS581G-02T
Contextual Info: ICS581-01, -02 Zero-Delay Glitch-Free Clock Multiplexer Description Features The ICS581-01 and ICS581-02 are glitch free, Phase Locked Loop PLL based clock multiplexers (mux) with zero delay from input to output. They each have 4 low skew outputs which can be

BUT20

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS04-213 48 -1 E ASSP Single Serial Input PLL Frequency Synthesizer On-Chip prescaler MB15C02 • DESCRIPTION T he Fujitsu M B15C 02 is a serial input Phase Locked Loop PLL freq ue n cy syn the sizer w ith a prescaler. A 64/65

PL671-02

Contextual Info: PL671-02 PicoEMI T M Spread Spectrum Clock Generator FEATURES PIN CONFIGURATION PDB^, CLK1 1 GND 2 FIN 3 PL671-02 • Advanced programmable PLL with Spread Spectrum  Reference Clock input o 1MHz to 200MHz  Output Frequency o <200MHz  Two programmable I/O pins

tc9137p

Abstract: TC9137BP TD6301AP E310 fet tc9137 td6104 td6301 td6301ap toshiba E310D TC9137BF
Contextual Info: 't O S H ^ T e LECTRONIC „ _ 02 D e | ciQc17E47~0017ciDci o | -. — • ; T-5o"n C-MOS LSI FOR STATIC TYPE DIGITAL TUNING SYSTEM. Unit in mm TC9137BP/BF are LSI for PLL synthesizer type digital tuning system with PLL circuit and control « circuit centralized'into one chip.

ICS507-01

Abstract: ICS507-02 ICS507M-01 ICS507M-01I ICS507M-01T MAN09
Contextual Info: ICS507-01/02 PECL Clock Synthesizer Description Features The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz or other high speed differential PECL clock output from a low frequency crystal input. Using Phase-LockedLoop (PLL) techniques, the devices use a standard

Contextual Info: ICS507-01/02 PECL Clock Synthesizer Description Features The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz or other high speed differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard