PIN DIAGRAM FORA DECODER Search Results

ic 74ls48 and 7 segment

Abstract: 74LS48PC decoder 74LS48
Contextual Info: 48 CO NNECTIO N DIAGRAM PINOUT A 54/7448y 54LS/74LS48^ ao[T BCD TO 7-SEGMENT DECODER DESCRIPTION — The '48 translates fo u r lines of BCD 8421 Input data into the 7-segment numeral code and provides seven corresponding outputs having pull-up resistors, as opposed to totem pole pull-ups. These outputs

BU9437AKV

Abstract: BU9437AKV-1 TSZ22111 SD Card connect USB Host MP3 decoder
Contextual Info: TYPE PRODUCTS PAGE SEM ICONDUCTO R LSI OStructure OProduct name O T yp e OApplications OFunctions BU9437AKV 1/4 Silicon Monolithic integrated circuit USB host W M A+M P3 Decoder LSI BU9437AKV Audio products, etc. BU9437AKV is W M A+M P3 decoder IC which contains USB host and SD card l/F, audio DAC,

ic MT8870

Abstract: ST88C870 MT8870 dtmf decoder TI 18L ST88C870CP18 MT8870 de dtmf decoder mt8870 ic
Contextual Info: STARTECH giSt \ Preliminary \ ' ' An 26* EX^IRCompany ST88C870 Printed August 3, 1995 INTEGRATED DTMF RECEIVER SOIC Package DESCRIPTION The ST88C870 is a complete DTMF receiver integrat­ ing both the bandsplit filter and digital decoder func­ tions. The filter section uses switched capacitor

ST Microelectronics battery

Contextual Info: M40Z300 M40Z300V SGS-THOMSON [M D M [iL[iO T M O (§ S NVRAM CONTROLLER for 1Mb to 16Mb LPSRAM PRELIMINARY DATA CONVERT LOW POWER SRAMs into NVRAMs PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION when Vcc is OUT-OF-TOLERANCE

icc3 icc1

Contextual Info: ^EDI EDI8464C/LP/P Ele ctronic D *dgrt$ Inc. High Speed 256K Monolithic SRAM 64Kx4 Static RAM CMOS, High Speed Monolithic Features The EDI8464C/LP/P is a high performance CMOS Static RAM organized as 64Kx4 and available in both standard power C , low power with data retention (LP)

Contextual Info: 8020 MCC Manchester Code Converter November 1989 Features Low Power CMOS Technology with Single 5V Supply m Compatible with IEEE 802.3/Ethernet 10BASE5 , IEEE802.3/Cheapernet (10BASE2) and Ethernet Rev. 1 Specifications 20 pin DIP A PLCC Packages • Compatible with 8003 ELDd6, 8005 Advanced

Contextual Info: SME D MÖM07D7 GGOlGbb l b 3 • ICT I C T INC 'T tft'tf-V 'J , INC. PEEL 22CV1OA-15/PEEL 22CV1OAL-15 CMOS Programmable Electrically Erasable Logic Device Features Advanced CMOS EEPROM Technology Architectural Flexibility — 132 product term x 44 input AND array

gyrator

Contextual Info: 12E P LE SS EY SEMICONDUCTORS D 722GS13 Q0QC] 4 4 4 4 A PLESSEY w Semiconductors . • p T J -u SL486 INFRA RED REMOTE CONTROL PREAMPLIFIER The SL486 is a high gain preamplifier designed to form an interface between an infra-red receiving diode and the digital

AND8005/D

Contextual Info: 8023A MCC Manchester Code Converter November 1989 Features Description • Compatible with IEEE 802.3 /Ethernet 10BASE5 , The SEEQ 8023A Manchester Code Converter chip pro­ vides the Manchester data encoding and decoding func­ tions of the Ethernet Local Area Network physical layer. It

MK5380

Abstract: Mostek DTMF
Contextual Info: SC11289 DTMF Transceiver r SIERRA SEMICONDUCTOR FEATURES □ DTMF Generator and Receiver on one chip □ CMOS single 5 Volt operation □ Uses inexpensive 3.579545MHz crystal The SCI 1289 is a complete Dual Tone Multiple Frequency DTMF Transceiver that can both generate

wireless intercom

Abstract: MX465 tele 539
Contextual Info: M X* CUM, INC. MiXed Signal ICs D A T A B U L L E T IN Low Voltage CTCSS Encoder/Decoder MX465 w ith TX/RX A udio Filters Document #20480143.003 ApriM 996 Preliminary Information Meets TlA/ElA-603 Standards 47 CTCSS Tones + Notone MX*COM MiXed Signal CMOS

16C450 DIP IC EXAR

Abstract: ST16C650A 16C450 isa circuits The650 ST16C550 ST16C650ACJ44 ST16C650ACP40 ST16C650ACQ48 ST16C650AIJ44 ST16C650AIP40
Contextual Info: ST16C650A UART WITH 32-BYTE FIFO’s AND INFRARED IrDA ENCODER/DECODER r GENERAL DESCRIPTION The ST16C650A*1 is a universal asynchronous receiver and transmitter (UART) and is pin compatible with the ST 16C550 UART. The 650A is an enhanced UART with 32 byte FIFO’s, automatic hardware/software flow control,

Contextual Info: Lattice pLSI 1016/883 programmable Large Scale Integration High-Density Programmable Logic Features Functional Block Diagram • PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — MIL-STD-883 Version of the pLS11016 High-Speed Global Interconnects 32 I/O Pins, Four Dedicated Inputs

Contextual Info: o n r m TECHNOLOGY LTC1235 M icroprocessor Supervisory C ircuit FCO TUR C S D C S C R IP T IO n • Guaranteed Reset Assertion at Vcc = 1V ■ 1.5mA Maximum Supply Current ■ Fast 35ns Max. Onboard Gating of RAM Chip Enable Signals ■ Conditional Battery Backup Extends Battery Life

ic 74 LS 138 DECODER data sheet

Abstract: TNC 24 mk 2 uln 298 80C03 84C30A W233
Contextual Info: Full Ouplex 84C30A 4-Port Ethernet Controller Technology Incorporated PRELIMINARY September 1995 Features • Low Power CMOS Technology I The Following A dditional Features can be Programmed fo r the 84C30A - 64 b it M ulticast Filter - Reports Status o f “SQE" During Transmits

Contextual Info: SME D 4 Ö M 0 7 D 7 OOOlGSfc. 214 B I I C T I C T INC , INC. - P M 6 ' 1 ^ - 0 1 PEEL 22CV10-25 CMOS Programmable Electrically Erasable Logic Device Features Archltectural Flexibility — 132 product term x 44 input AND array

Contextual Info: M a y 1988 HgL Micro Linear PRELIMINARY ML4421 Data Quantizer GENERAL DESCRIPTION FEATURES T h e M L4421 Data Q u a n tize r is a low noise, w id e b a n d , bipo­ lar m onolithic IC designed sp ecifically for signal recovery applications in fiber optic receiver system s. T h e M L4421 is

2SC256K

Abstract: 28C256K
Contextual Info: 28C256K Timer E 2 2 5 6 K Electrically Erasable P R O M October 1989 Description Features • CM O S Technology ■ Lo w P ow er • 60 mA A ctive • 150 fiA S tandby ■ Page W rite M ode • • ■ ■ SEEQ's 28C256K is a CMOS 5V only, 32Kx 8 Electrically

Contextual Info: Full Duplex ¡SI 84C300A ^ 4-Port Fast Ethernet Controller HURBCANE Technology Incorporated _ September 1995 PR ELIM IN A R Y Features • Low Power CMOS Technology ■ The Following A ddltional Features can be Programmed for the 84C300A

Contextual Info: •HYUNDAI H Y 5 1 1 6 1 0 0 S e r ie s 16Mx1-btt C M O S D R A M DESCRIPTION "The HY5116100 is the new generation and fast dynamic RAM organized 16,777,216x 1-bit. The HY5116100 utilizes Hyundai's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating

Contextual Info: A/VX-COM, INC. MX709 Voice Store Retrieve CVSD Codec FEATURES: APPLICATIONS: • • • • • • Digital Speech Communications • Digital Scrambling • Voice Message Mailbox • Speech Analysis • Voice Multiplexing • Speech Compression Delta Modulation Encoding

Philips PE 1938

Contextual Info: Philips Com ponents-Signetics Application Note Date o f Issue June 1986 AN23 P L S 1 6 8 /1 6 8 A p r im e r Rev. Date Programmable Logic Devices INTRODUCTION THE PLS168/168A is a bipolar Programmable Logic Sequencer as shown in Figure 1 , which consists of 12 inputs, a 48

ABO-20 L

Abstract: 1mx1 DRAM
Contextual Info: H Y 5 1 1 6 1 0 0 • H Y U N D A I S e r ie s 16Mx 1-bit CMOS DRAM DESCRIPTION The HY5116100 is the new generation and fast dynamic RAM organized 16,777,216x 1-bit. Ttie HY5116100 utilizes Hyundai's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating

Contextual Info: HY534256A Series “ H Y U N D A I 256KX 4-bit CMOS DRAM DESCRIPTION ITie HY534256A is the 2nd generation and fast dynamic RAM organized 262,144 x 4-bit. The HY534256A utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating