PHY13 Search Results

sem 2106

Abstract: SR5690 Northbridge Southbridge PCIe Bridge RD890 5650 ati ACC MICRO 2178 Index
Contextual Info: AMD SR5690/5670/5650 Register Reference Guide Publication # 43871 Issue Date: May 2012 Revision: 3.03 Trademarks AMD, the AMD Arrow logo, ATI, and combinations thereof, are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.

Atlas V quantum

Abstract: 132217 RCA-Y PM7324 Atlas IV quantum wsa0
Contextual Info: PM7324 S/UNI-ATLAS S/UNI-ATLAS DATASHEET PMC-1971154 ISSUE 7 S/UNI-ATM LAYER SOLUTION PM7324 S/UNI-ATLAS SATURN USER NETWORK INTERFACE ATM LAYER SOLUTION DATASHEET ISSUE 7: JANUARY, 2000 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

74HC

Abstract: DMP16 NJU3101 NJU3101D NJU3101M
Contextual Info: NJU3101 PRELIMINARY 4-BIT SINGLE CHIP TINY CONTROLLER • GENERAL DESCRIPTION The NJU3101 is the C-MOS 4-bit Single Chip Tiny Controller consisting of the 4-bit CPU Core, Input / Output Selectable I/O ports, Program ROM, Data RAM, and Oscillator Circuit CR or Ceramic or X'tal . It is packaged

peo 111

Abstract: 74HC NJU3102 NJU3102G NJU3102L
Contextual Info: NJU3102 PRELIMINARY 4-BIT SINGLE C H IP T IN Y CO NTRO LLER • PACKAGE OUTLINE GENERAL DESCRIPTION The NJU3102 is the C-M O S 4-bit Single Chip Tiny Controller consisted o f the 4-bit CPU Core, Input / O utput Selectable I/O ports, Program ROM, Data RAM, and

SMD fuse P110

Abstract: 74c914 transistor b733 transistor SMD p113 EPSON C691 MAIN npn transistor smd w19 smd diode c539 transistor b771 transistor c1015 transistor c1008 011
Contextual Info: 4 3 Figure 1: 2 1 ML300 CPU Table 1: ML300 CPU Virtex-II Pro Based Virtex-II Pro Based Block Diagram Table of Contents D D Infiniband HSSCD2 Dual Gig-E Fiber (Quad) Serial ATA (Dual) Sheet 1: Sheet 2: Sheet 3: Sheet 4: Sheet 5: Sheet 6: Sheet 7: Sheet 8:

43 0225h display module

Abstract: 0221H ADM6926
Contextual Info: Data Sheet, Rev. 1.03, September 2005 ADM6926 26 Port 10/100 Mbit/s Ethernet Switch Controller ADM6926 Communication CPE N e v e r s t o p t h i n k i n g . Edition 2005-09-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany

3504F

Abstract: INJU3504L NJU3504 NJU3504L PHY10 QFP-44 cmos schmit ml185
Contextual Info: NJU3504 PRELIMINARY 4-BIT SINGLE CHIP M ICRO CO NTRO LLER • GENERAL DESCRIPTION The NJU3504 is the C-MOS 4-bit Single Chip Micro Controller consisted of the 4-bit CPU Core, Input / Output Selectable I/O ports, Program ROM, Data RAM, Dual Timer/Counter, 8-bit Serial Interface, 8-bit A/D Converter,

MSB77-7

Abstract: MSB77 kje t9 kje x3 PJO 186 NJU3504 7D75 lfh 1001 3504F QFP-44
Contextual Info: • • • • • • 8 tf-y S!5> H >J h A/D sa-Mi * « * ï f ï lS f n f al> T Vf tïj>21 o o ü a s ft^ 5 : « ABS • SW&fcgH 4 { » » , ÿ - fv l X N v 2 , v 'JT JU A iÜ * • C-MOS W fi • W& QFP —44/SD I P —4 2 • • • • t s i * i

CBD10

Abstract: intel 7882 MARKING 09F PHAST-12E TXC-05802B TXC-05810 TXC-06212 SA 6356
Contextual Info: CUBIT-622 Device Multi-PHY CellBus Access Device TXC-05805 DESCRIPTION • 622 Mbit/s performance • UTOPIA Level 1/2 interface 8/16-bit with support for 64 ports • Tandem operation for two devices, supporting dual CellBus cell switching in load sharing or

EDLB4

Abstract: RY 485 ESA 132217 upc 451 PM7328 uaf41 LB07 R/nd 32
Contextual Info: PM7328 S/UNI-ATLAS-1K800 STANDARD PRODUCT DATASHEET ISSUE 2 ATM LAYER SOLUTION :4 3: 19 PM PMC-2010142 an ua ry ,2 00 3 11 PM7328 Su nd ay ,0 5J S/UNI-ATLAS-1K800 sil ico ne xp er to n ATM LAYER SOLUTION PROPRIETARY AND CONFIDENTIAL RELEASED ISSUE 2: JUNE 2001

abb ac drive circuit diagram

Contextual Info: DATASHEET PM PMC-971154 ISSUE 5 p r e li m in a r y STANDARD PRODUCT | ^ I \ # I • PMC-Sierra, Inc. PM7324 sajni-a t l a s S/UNI-A TM LA YER SOLUTION PM7324 S/UNI-ATLAS SATURN USER NETWORK INTERFACE ATM LAYER SOLUTION DATASHEET PRELIMINARY ISSUE 5: JAN 1999

NJU3102

Abstract: NJU3102G NJU3102L SDIP22 03CMP
Contextual Info: NJU3102 暫定資料 4 ビット 1 チップタイニーコントローラ • 概 要 ■ 外 NJU3102 は ROM, RAM, I/O ポートを内蔵した、 C-MOS プロセスによる 4 ビット 1 チップタイニーコントローラで す。 22 ピンパッケージに納められ、発振回路 CR 発振／水晶

superpro

Abstract: PHY10 NJU3000 MOG30 PHY12
Contextual Info: NJU3000 Series !"ADDRESSING PERIPHERAL REGISTER, RAM and ROM addresses are selected as follows. ① PERIPHERAL REGISTER ADDRESSING Peripheral Register address is selected by Y’-register Y’ in instructions of accessing the data in peripheral registers (PHYn). NJU3503/3504/3505/3553/3554/3555/3905 have two kinds of Peripheral

B1370

Abstract: NEC LD 8113 7 segment LD 1106 BS 132217 RCA-Y rdi17 PM7324 TDA 7284 NEC B1370 quantum atlas v 3.5
Contextual Info: PM7324 S/UNI-ATLAS PRELIMINARY STANDARD PRODUCT DATA SHEET PMC-971154 ISSUE 5 S/UNI-ATM LAYER SOLUTION PM7324 S/UNI-ATLAS SATURN USER NETWORK INTERFACE ATM LAYER SOLUTION DATASHEET PRELIMINARY ISSUE 5: JAN 1999 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

A01H

Abstract: 9FF MARKING T-RA18 SA 6356
Contextual Info: CUBIT-622 Device Multi-PHY CellBus Access Device TXC-05805 DESCRIPTION • 622 Mbit/s performance • UTOPIA Level 1/2 interface 8/16-bit with support for 64 ports • Tandem operation for two devices, supporting dual CellBus cell switching in load sharing or

Contextual Info: CUBIT-622 Device DATA SHEET PRODUCT PREVIEW DESCRIPTION FEATURES The CUBIT-622 device is a single-chip solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus architecture. Such systems are built from a number of CUBIT-3,

Atlas IV quantum

Contextual Info: PM7324 S/UNI-ATLAS PRELIMINARY STANDARD PRODUCT DATASHEET PMC-971154 ISSUE 6 S/UNI-ATM LAYER SOLUTION PM7324 S/UNI-ATLAS SATURN USER NETWORK INTERFACE ATM LAYER SOLUTION DATASHEET PRELIMINARY ISSUE 6: SEPTMEBER 1999 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

RCA 467

Abstract: transistor RCA 467 Atlas V quantum samsung LVDS 30 PIN 132217 RCA-Y PM7328 bss 108 jc 817
Contextual Info: PM7328 S/UNI-ATLAS-1K800 STANDARD PRODUCT DATASHEET PMC-2010142 ISSUE 2 ATM LAYER SOLUTION PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION DATASHEET PROPRIETARY AND CONFIDENTIAL RELEASED ISSUE 2: JUNE 2001 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

3504F

Abstract: NJU3504 NJU3504FA1 NJU3504L QFP44-A1
Contextual Info: NJU3504 PRELIMINARY 4-BIT SINGLE CHIP MICRO CONTROLLER • GENERAL DESCRIPTION The NJU3504 is the C-MOS 4-bit Single Chip Micro Controller consisting of the 4-bit CPU Core, Input / Output Selectable I/O ports, Program ROM, Data RAM, Dual Timer/Counter, 8-bit Serial Interface, 8-bit A/D Converter,

TXC-05804-MB

Abstract: sot marking code w17 W17 marking code sot 23
Contextual Info: CUBIT-3 Device CellBus Bus Switch TXC-05804 DATA SHEET CUBIT®-Pro The CUBIT-3™ is a single-chip VLSI solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus® architecture. Such systems are constructed from a number of CellBus devices, all

led display alarm clock ma 1042

Contextual Info: Semiconductor DATA BOOK C-MOS 4-BIT MICRO CONTROLLER NJU3000 Series VOLUME 2 Neu lapaziRadio Co.IicL [CAUTION] 1. NJRC strives to produce reliable and high quality semiconductors. NJRC's semiconductors are intended for specific applications and require proper maintenance

TLR324

Abstract: LDI 001 l4 tam TBA 427 D3101 147006c PH13 ZT rh 006c but79 CDU-F
Contextual Info: NJU3101 4 M"j Y 1 f 7 m n h u —=7 m i* m NJU3I011Ì, ROM, RAM, l / O - f - C - M O S ^ a - f e i. %4 t ' - y h I f 7 ^ - r - - 3 > /-t2 7 ì • V i'f g ts h f f l l S t l T L ' i l f c i Ì I , ìS Ìfc O T iA ffliiia - y - h P - 7 t t „ Ì 3 - r * ' 4 ' ^ # l t g | 3 p nn Ì IC 3 fliT « £ ;?ttfc ìtiiJ

irf 250n

Abstract: HJU3102G NJU3101 NJU3102 NJU3102L d 327 pai
Contextual Info: □ ''í CPU CO RE m CD » Ô o w Cl to CO o U o w H w m C/3 C/} PI H H Ô < • • • o 2; SK 1 S S sfc _ -rrf Üé SDIP/SOP 0 m» Cf i Si 1 m « a S ii i+ i ^ s S* 11 ^ • g» Ä 4Ì »£ !» * Et is s • 22 Si K. ^ * en Vj- <2 V -. ri vjl X n N I "

NJU3000

Abstract: XELTEK 3554
Contextual Info: NJU3000 シリーズ • インストラクションインデックス ADD A, M ADD A, #K AND A, M AND A, #K CALL addr CLA CLC CMP A, M CMP Y, #K DEC A DEC M DEC Y HLT INC A INC M INC Y JMP addr JPL addr LDI A, #K LDI X, #K LDI Y, #K NEG NOP OR A, M OR A, #K