PHY INTERFACE FOR THE PCI EXPRESS Search Results

FW533

Abstract: L-FW533
Contextual Info: FW533 PCI Express 1394a PHY/Link Open Host Controller Interface Product Brief Introduction The Agere Systems FW533 is specifically designed for PCI Express. It combines an OHCI open host controller interface with Agere’s TrueFIRE technology and a

XC3S500E

Abstract: reliability report of nxp PX1011A PX1011A-EL1 DO-DI-PCIEXP "network interface cards"
Contextual Info: 11 Endpoint PIPE v1.7 for PCI Express DS321 May 17, 2007 Product Specification Introduction LogiCORE Facts The Endpoint PIPE PHY Interface for PCI Express 1-lane core is a high-bandwidth scalable and reliable serial interconnect intellectual property building block

2n3904 c25

Abstract: 93c46 st NDS351N 93C46 AN1302 PC99 74VHC123
Contextual Info: AN1302 APPLICATION NOTE STE10/100A - PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY General Description The STE10/100A is a high performance, low power, 3.3V PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. The system diagram is

TCI D2S

Abstract: TCI D2S f BRA16 128-Byte CSR19 M1FD STMicroelectronics BET
Contextual Info: STE10/100 PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY PRODUCT PREVIEW 1.0 DESCRIPTION The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to

PAB1

Abstract: TCI D2S 93C46 PC99 PQFP128
Contextual Info: STE10/100A PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 3.3V 1.0 DESCRIPTION The STE10/100A is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to

PQFP128

Abstract: aui isolation transformer 10/100 BASE TRANSFORMERS LAN COMPONENTS a06 transistor 4-pin PAB1 stmicroelectronics "serial eeprom" 93C46 AD-29 PC99
Contextual Info: STE10/100A PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 3.3V 1.0 DESCRIPTION The STE10/100A is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to

PQFP128

Abstract: 93C46 PC99 TCI D2S
Contextual Info: STE10/100 PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V PRODUCT PREVIEW 1.0 DESCRIPTION The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to

aui isolation transformer

Abstract: TCI D2S f stmicroelectronics "serial eeprom" 93C46 AD-29 PC99 PQFP128 TCI D2S ad1035
Contextual Info: STE10/100A PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 3.3V PRODUCT PREVIEW 1.0 DESCRIPTION The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to

IEEE802.3 Clause 45

Abstract: PAB1 93C46 PC99 PQFP128 bra4
Contextual Info: STE10/100A PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 3.3V PRODUCT PREVIEW 1.0 DESCRIPTION The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to

TCI D2S

Abstract: bra1015
Contextual Info: STE10/100A PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 3.3V PRODUCT PREVIEW 1.0 DESCRIPTION The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to

TCI D2S

Abstract: DSA008 TCI D2S f PAB1 93C46 AD-29 PC99 PQFP128
Contextual Info: STE10/100A PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 3.3V PRODUCT PREVIEW 1.0 DESCRIPTION The STE10/100A is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to

AN10373

Abstract: ddr phy interface TI-XIO1100 ddr phy PX1011A XIO1100 TIXIO1100 analog buffers Texas instruments 8-bit altera board
Contextual Info: External PHY Support in PCI Express MegaCore Functions May 2007, ver. 1.0 Introduction Application Note 443 The PCI Express Compiler generates customized PCI Express MegaCore functions that you can use to design PCI Express endpoints. The PCI Express MegaCore functions are compliant with PCI Express Base

MO-205

Abstract: PX1011B dc/tx/1/2/1257/PX1011B
Contextual Info: PX1011B PCI Express stand-alone X1 PHY Rev. 02 — 19 March 2008 Product data sheet 1. General description The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer PHY that handles the low level PCI Express protocol and signaling. The

PHY Interface for the PCI Express

Abstract: PX1041A MO-205 sot631 PX1041A-EL1
Contextual Info: PX1041A PCI Express stand-alone X4 PHY Rev. 01 — 21 June 2007 Objective data sheet 1. General description The PX1041A is a high-performance, low-power, four-lane PCI Express electrical PHYsical layer PHY that handles the low level PCI Express protocol and signaling. The

Contextual Info: PX1011B PCI Express stand-alone X1 PHY Rev. 01 — 13 February 2008 Objective data sheet 1. General description The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer PHY that handles the low level PCI Express protocol and signaling. The

marking code E5 SMD ic

Abstract: smd marking code g8 smd marking g8 phy interface for the PCI Express MO-205 PX1011B MARKING G3 5pin
Contextual Info: PX1011B PCI Express stand-alone X1 PHY Rev. 04 — 4 September 2009 Product data sheet 1. General description The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer PHY that handles the low level PCI Express protocol and signaling. The

smd marking g8

Abstract: smd marking e5 5Pin smd transistor marking j6 SMD 5pin code E2 marking code E5 SMD ic smd marking code g8 Diode smd f6 PHY Interface for the PCI Express marking code C3 SMD ic smd transistor s2p
Contextual Info: PX1011B PCI Express stand-alone X1 PHY Rev. 03 — 20 October 2008 Product data sheet 1. General description The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer PHY that handles the low level PCI Express protocol and signaling. The

Contextual Info: Genesys Logic, Inc. GigaCourierTM/PHY GL230 PCI EXPRESSTM PIPE PHY Layer Controller Datasheet Preliminary Revision 0.70 Jun. 21, 2003 GigaCourierTM/PHY GL230 PCI ExpressTM PIPE PHY Controller Copyright: Copyright 2003 Genesys Logic Incorporated. All rights reserved. No part of the materials may be

history of rome

Abstract: PHY Interface for the PCI Express AEC-Q100 MO-205 PX1011B MARKING CODE E5 NXP
Contextual Info: PX1011B PCI Express stand-alone X1 PHY Rev. 5 — 18 April 2011 Product data sheet 1. General description The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer PHY that handles the low level PCI Express protocol and signaling. The

Contextual Info: PX1011B PCI Express stand-alone X1 PHY Rev. 6 — 27 June 2011 Product data sheet 1. General description The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer PHY that handles the low level PCI Express protocol and signaling. The

XI01100

Abstract: TSMC 90nm application on PCI parallel interface DDR PHY ASIC PCI express design pci non-transparent bridge EP2C35 XIO1100 TI-XIO1100 sllb100
Contextual Info: White Paper Low-Cost FPGA Solution for PCI Express Implementation Introduction PCI Express is rapidly establishing itself as the successor to PCI, providing higher performance, increased flexibility, and scalability for next-generation systems, as well as maintaining software compatibility with existing PCI

82557 user manual

Abstract: 82557 intel 82557 intel 4101 8086 with eprom PHY-100 SEEQ eprom BNC-RJ 28F010 LAN557
Contextual Info: E AP-369 APPLICATION NOTE LAN557 Hardware/Software Interface Definition August 1996 Order Number: 644863-002 12/6/96 11:01 AM 64486302.DOC INTEL CONFIDENTIAL until publication date Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

MoSys

Abstract: MoSys 1T sram MoSys pcie verification for pci express "PCI Express" CHIP EXPRESS serdes ip vlsi design physical verification MoSys sram embedded
Contextual Info: MoSys Announces Availability of 40nm PCI Express 2.0 PHY Proven Interoperability with Industry Standard PCI Express Controller from Denali Software Streamlines IO Sub-System Design SUNNYVALE, CA, November 2, 2009 — MoSys, Inc., a leading supplier of differentiated high

PI7C9X1011

Abstract: beacon transmitter PHY interface for PCI EXPRESS CHIP EXPRESS
Contextual Info: Product: Part Number: PCI Express Single PHY PI7C9X1011 Product Description Product Features The PI7C9X1011 is a single-lane PCI Express electrical PHYsical PHY layer chip, which operates at a high speed of 2.5 Gbps for serial link transmissions and operates at