PHL 7 S Search Results

RPM-20CT

Abstract: PC-10 PC13 PH516LR
Contextual Info: - 310- ? ^ % tt £ £ VXH £ VHL m ax íx m ax (Ix) PH 516H C (L) a fi u •/ > a /i. (-"rag • ft ¥ í¿ Vcc iV ) W. tpLH typ {¡ts) ft # m t PHL typ in s) 14 Ev (1x) (7'„ = 25°Ci (T „ = 25°C) sf w‘ — ÿ jgt fä Rl (Cl) f t 7« 1 Vcc (V) ty p !nm)

ci 4030

Abstract: 4030B ST 4030 BE CO164 4030BE
Contextual Info: S G S-THOnSON G7C » I 7 ^ 0 3 7 OOITOS 5 I ' cos/mos y r r r ^ INTEGRATED | o k ; hcc/hcf « b CIRCUIT •_ . 4 1C 0 8 7 2 5 _ T - Ÿ 3 - Z } QUAD EXCLUSIVE - OR GATE • • • • • • • • M ED IU M -S PEE D O P E R A T IO N - t PHL= t PLH= 60 ns TYP. @ CL= 50 pF and V DD- V SS= 10V

Contextual Info: 74HC/HCT175 MSI Q UAD D-TYPE FLIP-FLOP W ITH RESET; POSITIVE-EDGE TRIGGER FEATURES T Y P IC A L PARAM ETER SYMBOL Four edge-triggered D flip-flops Output capability: standard I q c category: MSI propag atio n delay CP to Q n< Q ji MR to Q n t PHL The 7 4 H C /H C T 1 7 5 have fo u r edgetriggered, D -type flip -flo p s w ith

Contextual Info: — 4S II x IN A o IN B o - = F • tstb »a « a * # "7 A b is j- tr micomm tf tPLH IN -> OUT tPHL (IN -> OUT ) tPLH t PHL ■ VDD 5V 10V 15V 5V in v & ■ lE H B W J jN A N D y -h y -h NAND 2 1 5 "/ h * L >OUT X m -X4 y + y r m ■ — 2 Input N A N D G ate

TDA 7378

Abstract: TDA 7822 block diagram baugh-wooley multiplier tda 12062 equivalent for tda 4858 ic free transistor equivalent book STD-80 4856 a 14 PIN DIP W908 LSI CMOS Technology
Contextual Info: D • A • T • A • B • O • O • K STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library April 1997 V SAMSUNG SAMSUNG ASIC STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library Data Book  1997 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 - D32Q0, OCTOBER 1989 - REVISED APRIL 1993 • ■ I ■ I * Inputs Are TTL-Voltage Compatible * New Flow>Through Architecture Optimizes PCB Layout * Center-Pin V ^c and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: SN54AHC157, SN74AHC157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS SCLS345 - MAY 1996 Operating Range 2-V to 5.5-V Vcc EPIC Enhanced-Performance Implanted CMOS Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outllne

Contextual Info: SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS S CLS258C - DECEM BER 1995 - REVISED JULY 1996 Operating Range 2-V to 5.5-V Vqc E P IC * Enhanced-Performance Implanted CMOS Process SN54AMC138 . . . J O R W PACKAGE SN74AHC138 . . . D, DB, N, OR PW PACKAGE

Contextual Info: SN54AS181B, SN74AS181A ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS SDAS209B - DECEMBER 1962 - REVISED DECEMBER 1994 Full Look Ahead or High-Speed Operations on Long Words Arithmetic Operating Modes: - Addition - Subtraction - Shift Operand A One Position - Magnitude Comparison

74AC11151

Contextual Info: 74AC11151 1-0F-8 DATA SELECTOR/MULTIPLEXER D3348, JUNE 1989 - REVISED APRIL 1993 * 8-Llneto 1-Line Multiplexers Can Perform as Boolean Function Generators, Parallel-to-Serial Converters, or Data Source Selectors □ OR N PACKAGE TOP VIEW DO [ 1 OË[ 2 Y [ 3

74HCT190

Contextual Info: GD54/74HC190, GD54/74HCT190 SYNCHRONOUS DECADE UP/DOWN COUNTER W ITH MODE CONTROL G e n eral D escrip tion These devices are identical in pinout to the Pin C o n fig u ra tio n 5 4 / 7 4 L S 1 9 0 . T his s y n c h ro n o u s , re v e rs ib le , up/dow n BCD counter can be preset by applying the

Contextual Info: MOE » HARRIS SEflICÔN» SECTOR ill U U HARRIS H A R R IS S E M I C O N D U C T O R RCA QE • 4302271 0034300 5 1 HAS Military & Aerospace Products IN TERSIL HCTS190MS T-H5-23-OH 5 iE 13] RC High-Reliability Radiation-Hardened High-Speed CM OS/SOS Synchronous

74LS181

Contextual Info: PIN CONFIGURATION SPEED/PACKAGE AVAILABILITY 54 F,W 74 A A,F,W PACKAGE LOGIC DIAGRAM •E H |V C C 'E e^enq; I odo[T I SWITCHING CHARACTERISTICS VCC = 5V. TA - 25° C TO OUTPUT tPLH 'PHL Low-to-high High-to-low Data £Even 40 45 60 68 tPLH »PHL Low-to-high

74LS65

Contextual Info: 8-B it Bus Front-Loading-Latch Transceivers SN54/74LS651 SN54/74LS653 SN54/74LS652 SN54/74LS654 Ordering Information Features/Benefits • Bidirectional bus transceivers and registers PART NUMBER • Independent registers tor A and B buses • Real-time data transfer or stored data transfer

74AS181B

Abstract: 74AS181
Contextual Info: SN54AS181 A, SN54AS881A, SN74AS181A, SN74AS881A ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS D 2 6 6 1 , DECEMBER 1 9 8 2 -R E V IS E D M A Y 1 9 8 6 Package Options Include the 'AS181A in Compact 300-mil or Standard 600-mil Packages. The 'AS881A is Offered in 300-mil

74LS648

Abstract: 74LS647 74LS646 ls646 74LS646 buffer 74LS649 buffer sn74ls649ns 74LS649 SN74LS649 SN74LS647
Contextual Info: 8 -B it Bus Front-Loading-Latch Transceivers SN54/74LS646 SN54/74LS648 SN54/74LS647 SN54/74LS649 O rdering Inform ation F e atu res /B e n efits • Bidirectional bus transceivers and registers PART NUMBER • Independent registers for A and B buses • Real-time data transfer or stored data transfer

bcd adder

Contextual Info: SPEED/PACKAGE AVAILABILITY 54 F,W 74 TRUTH TABLE B INPUTS PIN CONFIGURATION OUTPUT 8* R Q H L H L H H L L Qo B,F,W PACKAGE H L Hi H - h ig h level L - lo w level Q Q -th e level o f Q b e fo re these in p u t c o n d itio n s w ere e sta b ­ lished •For la tch e s w ith d o u b le S inputs:

z814

Abstract: Z8148
Contextual Info: AmZ8148 Chip Select Address Decoder With Acknowledge DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • One-of-Eight Decoder provides eight chip select outputs • Acknowledge output responds to enables and acknowledge input command • Open-collector Acknowledge output for wired-OR application

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 - D3200, OCTOBER 1989 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: 74HC/HCT181 MSI 4-BIT A R IT H M E T IC LO G IC U N IT FEATURES • • • • • Full carry look-ahead for high-speed arithmetic operation on long words Provides 16 arithmetic operations: add, subtract, compare, double, plus 12 others Provides all 16 logic operations of

Contextual Info: GD54/74HC354, GD54/74HCT354 DUAL 4-T0-1 LINE MULTIPLEXERS WITH LATCHES & 3-STATE OUTPUTS General Description These devices are identical in pinout to the 5 4 /7 4 L S 3 5 4 . They contain full on-chip binary decoding to select one of eight data sources, deter­

74LS90 pin configuration

Abstract: configuration 74ls90
Contextual Info: SPEED/PACKAGE AVAILABILITY 54 F,W S4LS F,W BLOCK DIAGRAM 54LS/74LS PIN CONFIGURATION 74 A,F 74LS A,F DESCRIPTION This monolithic counter contains four mas­ ter-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the

74LS357

Abstract: SC14113 31003 ha V69D ic ttl 74ls LS357
Contextual Info: TYPES SN54LS354, SN54LS355, SN54LS356, SN54LS357, SN74LS354, SN74LS355, SN74LS356, SN74LS357 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS/REGISTERS _ D 2 5 4 4 , JULY 19 7 9 -R E V IS E D APRIL 1 9 8 5 SN 54LS354, SN 54LS355 . . . J PACKAGE

D3455

Contextual Info: 74ACT11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER SCAS106A- D3455, FEBRUARY 1990 - REVISED APRIL 1993 DW OR N PACKAGE TOP VIEW * Inputs Are TTL-Voltage Compatible * Single Down/Up Count Control Line * Look-Ahead Circuitry Enhances Speed of Cascaded Counters