PECL 554 Search Results

ICS553

Abstract: ICS552-02 ICS554-01 ICS554G-01I ICS554G-01IT MAN09
Contextual Info: ICS554-01 LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01 is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. For parts which do not require PECL

ICS554-01

Abstract: ICS552-02 ICS553 ICS554G-01 ICS554G-01T MAN09
Contextual Info: ICS554-01 LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01 is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. For parts which do not require PECL

Contextual Info: DATA SHEET ICS554-01A ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUTLOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our

Contextual Info: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL

ICS552-02

Abstract: ICS553 ICS554-01 ICS554-01A 554G-01AILF
Contextual Info: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of IDT’s Clock BlocksTM family, this is our lowest skew PECL

Contextual Info: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL

ics554 clock buffer

Abstract: ICS552-02 ICS553 ICS554-01 ICS554-01A 13Q3
Contextual Info: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of IDT’s Clock BlocksTM family, this is our lowest skew PECL

MK74CBxxx

Abstract: ICS552-02 ICS553 ICS554-01 ICS554-01A
Contextual Info: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL

Contextual Info: ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. The ICS554-01A is

554-01a

Abstract: ICS552-02 ICS553 ICS554-01 ICS554-01A ICS554GI-01A ICS554GI-01AT 101904
Contextual Info: ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. The ICS554-01A is

Contextual Info: ICS554-01 EOL - DEVICE NOT RECOMMENDED FOR NEW DESIGNS LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01 is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew

ICS552-02

Abstract: ICS553 ICS554-01 ICS554G-01 ICS554G-01T MAN09
Contextual Info: ICS554-01 P R E L I M I N A RY I N F O R M AT I O N LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01 is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew

Contextual Info: * S O NET OC-12/OC-3 CLO C K SYNTHESIZER SYNERGY SEMICONDUCTOR Clockworks SY89426 DESCRIPTION FEATURES • Single chip source for 622.08MHz and 155.52MHz clocks ■ 622.08MHz output is differential PECL, 155.52MHz output is single-ended PECL ■ TTL/CMOS compatible inputs and reference output

S2046B

Abstract: S2050 S2050A-3
Contextual Info: DEVICE SPECIFICATION S2046/S2050 S2046/S2050 GIGABIT ETHERNET CHIPSET GIGABIT PECL ETHERNET CHIPSET BiCMOS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES • Functionally compliant with the 802.3z specification • S2046 transmitter incorporates phase-locked

D10-19

Abstract: S2042 S2043 S2042B-05 14D19
Contextual Info: PRELIMINARY DEVICE SPECIFICATION S2042/S2043 S2042/S2043 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK SERIAL GENERATOR HIGH PERFORMANCE INTERFACE CIRCUITS GENERAL DESCRIPTION FEATURES • Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol

NEC TOSA 10G

Abstract: laser stm-64 10gbps 2dbm TOSA 10G 10Gbps TOSAs 400C 850C ADN2525 STM-64 "Voltage to Current Converter" 850c be 331
Contextual Info: 10Gbps Active Back-match, Differential Laser Diode Driver ADN2525 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Up to 10.7Gbps operation Very low power: Icc=157mA Typical 24 ps rise/fall times PECL/CML compatible data inputs Bias current range: 10mA to 100mA

S2044

Abstract: D10-19 S2045
Contextual Info: PRELIMINARY DEVICE SPECIFICATION S2044/S2045 S2044/S2045 GLM COMPLIANT SERIAL INTERFACE CIRCUITS GLM COMPLIANT SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK GENERATOR FEATURES GENERAL DESCRIPTION • Complies with the electrical and link levels of the Gigabaud Link Module GLM specification

HD-SDI deserializer 16 bit parallel

Abstract: HD-SDI serializer 16 bit parallel S8401 HD-SDI deserializer 8 bit parallel S8401QF DIVIDE-BY-20 S8501 D4 Package parallel to HD-SDI 35-/parallel to HD-SDI
Contextual Info: DEVICE SPECIFICATION HIGH DEFINITION SERIAL DIGITAL INTERFACE HD-SDI CHIPSET HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET BiCMOS PECL CLOCK GENERATOR FEATURES • • • • • • • • • • • • S8401/S8501 S8401/S8501 GENERAL DESCRIPTION

Contextual Info: VM 5210M • High Performance - Rise/Fall Times = 6.5 ns Typical into 1 nH Head - Input Capacitance = 10 pF Typical - Input Noise = 0.52 nV/VHz Typical - Head Inductance Range = 0 .2 -1 .5 nH - Voltage Gain = 150 V/V - Olher Options Available • PECL Write Data Lines

Contextual Info: VM 522015C August, 1995 CON NECTION DIAGRAM • High Performance - Rise/Fall Times = 4 ns Typical into 600 nH Head - Input Capacitance = 10 pF Typical - Input Noise = 0.65 nV/VHz Typical - Head Inductance Range = 400 - 800 nH - Voltage Gain = 150 V/V • PECL Write Data Lines

5-2736

Abstract: LU3X51FT transistor 5-2736 MR30 MR31 REF10 LC10 LC100 LU3M38 manchester
Contextual Info: Data Sheet July 2000 FASTCAT TM LU3X51FT Ethernet Transceiver 10/100Base-TX/FX Features 100 Mbits/s FX Transceiver 10 Mbits/s Transceiver • Compatible with IEEE 802.3u 100Base-FX standard ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL PECL

Contextual Info: * PR O G R A M M A B LE FR EQ U EN C Y SYNTHESIZER SYNERGY Clockworks SY89429V 25MHz to 400MHz SEMICONDUCTOR DESCRIPTION FEATURES • 3.3V and 5V power supply options ■ 25MHz to 400MHz differential PECL outputs ■ ±25ps peak-to-peak output jitter

ST 358

Abstract: "network interface cards"
Contextual Info: Advance Data Sheet October 1998 FASTCAT TM LU3X51FT Ethernet Transceiver 10/100Base-TX/FX Features 100 Mbits/s FX Transceiver 10 Mbits/s Transceiver • Compatible with IEEE 802.3u 100Base-FX standard ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL PECL

Contextual Info: 5420 series VCXO Module ICs with Built-in Varicap OVERVIEW The 5420 series are LV-PECL output VCXO ICs that provide a wide frequency pulling range. They employ bipolar oscillator circuit and recently developed varicap diode fabrication process that provides a low phase noise characteristic and a wide frequency pulling range