PCI EXPRESS TLP Search Results

wishbone

Abstract: genesys virtex 5
Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

PCI AHB DMA

Abstract: tsmc 0.18 axi bridge
Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

89HPES8T5A

Abstract: bc196 GE H11 A10
Contextual Info: 89HPES8T5A Data Sheet 8-Lane 5-Port PCI Express Switch Device Overview ◆ The 89HPES8T5A is a member of IDT’s PRECISE family of PCI Express switching solutions. The PES8T5A is an 8-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and

Contextual Info: 89HPES8T5A Data Sheet 8-Lane 5-Port PCI Express Switch ® Device Overview u The 89HPES8T5A is a member of IDT’s PRECISE family of PCI Express switching solutions. The PES8T5A is an 8-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and

89PES5T5

Contextual Info: 89PES5T5 Data Sheet 5-Lane 5-Port PCI Express Switch Device Overview ◆ The 89HPES5T5 is a member of IDT’s PRECISE family of PCI Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connectivity

PI7C9X130D

Abstract: Equivalent tlp 759 PI7C9X130 IC 74115
Contextual Info: PI7C9X130 PCI Express to PCI-X Reversible Bridge Revision 2.2 3545 North First Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 Fax: 408-435-1100 Internet: http://www.pericom.com 12-0241 PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE LIFE SUPPORT POLICY

10-lane serdes

Abstract: 89HPES10T4G2
Contextual Info: 89HPES10T4G2 Data Sheet 10-Lane 4-Port Gen2 PCI Express Switch ® Device Overview ◆ The 89HPES10T4G2 is a member of IDT’s PRECISE family of PCI Express® switching solutions. The PES10T4G2 is a 10-lane, 4-port Gen2 peripheral chip that performs PCI Express Base switching with a

Contextual Info:  Compliant with PCI Express Base Specification 1.1  Implements Transaction, Data CPXP-EPx8 PCI Express Endpoint Controller Megafunction with SoC Bridge Extensions for AMBA AXI Link, and Physical protocol layers in hardware  Supports x8 link width

PI7C9X20404SL

Abstract: 128-PIN IS24C04 PI7C9X20404 PI7C9X404
Contextual Info: PI7C9X20404SL PCI EXPRESS PACKET SWITCH DATASHEET REVISION 1.2 July 2009 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 FAX: 408-435-1100 Internet: http://www.pericom.com PI7C9X20404SL 4Port-4Lane PCI Express Switch

PI7C9X20505

Abstract: PI7C9X20505GP IS24C04
Contextual Info: PI7C9X20505GP PCI EXPRESS PACKET SWITCH DATASHEET REVISION 1.5 June 2009 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 FAX: 408-435-1100 Internet: http://www.pericom.com PI7C9X20505GP 5Port-5Lane PCI Express Switch GreenPacketTM Family

BUS22 B1

Abstract: PI7C9X20404 TLP 723 PI7C9X20404GP 148-PIN IS24C04 msi 7267 ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME
Contextual Info: PI7C9X20404GP PCI EXPRESS PACKET SWITCH DATASHEET REVISION 1.6 June 2009 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 FAX: 408-435-1100 Internet: http://www.pericom.com PI7C9X20404GP 4Port-4Lane PCI Express Switch GreenPacketTM Family

PI7C9X7954

Abstract: RS-424 128-PIN 16C550 uart 16c950
Contextual Info: PI7C9X7954 PCI Express Quad UART Datasheet Revision 1.3 September 2009 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 FAX: 408-435-1100 Internet: http://www.pericom.com 09-0088 PI7C9X7954 PCI Express® Quad UART Datasheet

RS-424

Abstract: rs424 PI7C9X7958 16c950 RS-458 N2049 16C550 PI7C7958 1-877-PERICOM
Contextual Info: PI7C9X7958 PCI Express Octal UART Datasheet Revision 1.4 March 2011 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 FAX: 408-435-1100 Internet: http://www.pericom.com 11-0039 PI7C9X7958 PCI Express® Octal UART Datasheet

Contextual Info: XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART APRIL 2011 REV. 1.0.2 GENERAL DESCRIPTION FEATURES The XR17V3521 V352 is a single chip 2-channel PCI Express (PCIe) UART (Universal Asynchronous Receiver and Transmitter), optimized for higher performance and lower power. The V352 serves as a

PI7C9X111

Abstract: PI7C9X111SL PI7C9X111SLBFDE TLP 6341 ID-01H B1B3H PI7C9X111S
Contextual Info: PI7C9X111SL PCI Express-to-PCI Reversible Bridge Revision 1.5 3545 North 1ST Street, San Jose, CA 95134 Phone: 1-877-PERICOM 1-877-737-4266 FAX: 1-408-435-1100 Internet: http://www.pericom.com PI7C9X111SL PCIe-to-PCI Reversible Bridge LIFE SUPPORT POLICY

pex8311 fpga interface

Abstract: PEX8311-AA66BCF PEX8311 8311-AA66BC pex8311aa66bcf interface of camera fpga pex8311-aa66 PEX8311-AA66BC Scatter-Gather
Contextual Info: . Version 1.2 2005 PEX 8311 PCI Express to Generic Local Bus Bridge Features PEX 8311 Key Features o PCI Express to Generic Local Bus Bridge o Root Complex and EndPoint Modes of Operation o Local Bus modes: - 32-bit address & 32-bit data C Mode - Multiplexed 32-bit address/data J Mode

400M

Abstract: XIO2200 XIO2200A
Contextual Info: XIO2200A PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY Data Manual Literature Number: SCPS154B March 5 2007 Printed on Recycled Paper Contents Section 1 2 3 Page XIO2200 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contextual Info: XIO2000 PCI Express to PCI Bus Translation Bridge Data Manual Literature Number: SCPS097B November 2005 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

Contextual Info: XIO2000 PCI Express to PCI Bus Translation Bridge Data Manual Literature Number: SCPS097B November 2005 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

XIO2001

Abstract: 169-Ball
Contextual Info: XIO2001 XIO2001 PCI Express to PCI Bus Translation Bridge Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not

AD27

Abstract: AD30 tlp 453
Contextual Info: XIO2001 XIO2001 PCI Express to PCI Bus Translation Bridge Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not

Contextual Info: Not Recommended for New Designs XIO2200A PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY Data Manual Literature Number: SCPS154C March 5 2007 − June 2011 Printed on Recycled Paper Not Recommended for New Designs Contents Section

PES24T6

Abstract: 89HPES24T6 simple switch block diagram
Contextual Info: 89HPES24T6 Product Brief 24-Lane 6-Port PCI Express Switch Device Overview Legacy Support – PCI compatible INTx emulation – Bus locking ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and

pcie X8

Abstract: pcie x4 89PES32T8 x8 encoder idt PCIE SWITCH chip
Contextual Info: 89PES32T8 Product Brief 32-Lane 8-Port PCI Express Switch Device Overview Legacy Support – PCI compatible INTx emulation – Bus locking ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and