PCI EXPRESS DIMENSIONS Search Results

CK410B

Abstract: PI6C20400 PI6C20800 PI6C21200 PI6C410B RW1N differential buffer for pci-express
Contextual Info: PI6C21900 PCI Express Gen II1:19 Geared Differential Buffer -17 and 2 Outputs Features Description • Phase jitter filter for PCIe Gen II application PI6C21900 is a PCI Express Gen II compliant, high-speed, low-noise PCI-Express and FBDIMM differential clock buffer designed to be

history of rome

Abstract: PHY Interface for the PCI Express AEC-Q100 MO-205 PX1011B MARKING CODE E5 NXP
Contextual Info: PX1011B PCI Express stand-alone X1 PHY Rev. 5 — 18 April 2011 Product data sheet 1. General description The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer PHY that handles the low level PCI Express protocol and signaling. The

Contextual Info: NCN3411 4-Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3 The NCN3411 is a 4−Channel differential SPDT switch designed to route PCI Express Gen3 signals. When used in a PCI Express application, the switch can handle up to two PCIe lanes. Due to the

932S421BGLF

Abstract: ICS9DB102 ICS952601 ICS954101
Contextual Info: DATASHEET ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function Description Features/Benefits 1-to-2 Zero-delay or fanout buffer for PCI Express.The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC

Contextual Info: ICS8741004I DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR General Description Features The ICS8741004I is a high performance Differential-to-LVDS/0.7V Differential Jitter HiPerClockS™ Attenuator designed for use in PCI Express™

MM60-52B1-B1-R850

Abstract: mm60ezh059b5 MM60-52B1-E1 SJ105222 mm60ezh039b5 SJ105221 MM60-52B1-B1
Contextual Info: COMPONENTS PRODUCT INFORMATION NEW Compatible with PCI Express Mini Card CONNECTOR MM60 Series MB-0147-3 February 2008 RoHS Compliant The MM60 series is a module socket compatible with specifications standardized by the PCI-SIG. Features „Compatible with the PCI Express Mini Card Electromechanical spec and can be

8741004AG

Abstract: 8741004AGT ICS741004 ICS8741004 ICS8741004AG
Contextual Info: ICS8741004 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR General Description Features The ICS8741004 is a high performance Differential-to-LVDS/0.7V Differential Jitter HiPerClockS™ Attenuator designed for use in PCI Express™

KPCIEX-T36-BK

Contextual Info: PCI EXPRESS EDGE CARD KYCON RoHS RoHS KPCIEX Series Documentation & Ordering Information Drawing Stock CofC Sample Email RFQ Kycon Part # KPCIEX-T36-BK Part Number Builder T 36 Mounting Options Pins KPCIEX Series KPCIEX Series PCI EXPRESS EDGE CARD CONNECTORS

SCDS269C

Contextual Info: TS2PCIE412 www.ti.com SCDS269C – MARCH 2009 – REVISED APRIL 2010 4-CHANNEL 8:16 MULTIPLEXER/DEMULTIPLEXER PCI EXPRESS SWITCH Check for Samples: TS2PCIE412 FEATURES 1 • • • PCIe Bus Multiplexing and Expansion Routing PCI Express Data and/or Display Port

RS-424

Abstract: rs424 PI7C9X7958 16c950 RS-458 N2049 16C550 PI7C7958 1-877-PERICOM
Contextual Info: PI7C9X7958 PCI Express Octal UART Datasheet Revision 1.4 March 2011 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, 1-877-737-4266 FAX: 408-435-1100 Internet: http://www.pericom.com 11-0039 PI7C9X7958 PCI Express® Octal UART Datasheet

Contextual Info: PCI EXPRESS CARD EDGE KYCON RoHS RoHS KPCIEX Series Documentation & Ordering Information Drawing Stock CofC Sample Email RFQ Kycon Part # KPCIEX-SM1-36BK Part Number Builder SM1 36 BK Mounting Options Pins Color KPCIEX Series KPCIEX Series Straddle Mount PCI Express Card Edge

Contextual Info: Crystal-to-HCSL 100MHz PCI EXPRESS Clock Synthesizer IDT8V41S104I DATA SHEET General Description Features The IDT8V41S104I is a PLL-based clock generator specifically designed for PCI EXPRESS™ Generation 3 applications. This device generates a 100MHz differential HCSL clock from an input

Contextual Info: XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART APRIL 2011 REV. 1.0.2 GENERAL DESCRIPTION FEATURES The XR17V3521 V352 is a single chip 2-channel PCI Express (PCIe) UART (Universal Asynchronous Receiver and Transmitter), optimized for higher performance and lower power. The V352 serves as a

XR17V352

Abstract: 0x4803
Contextual Info: XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART APRIL 2012 REV. 1.0.3 GENERAL DESCRIPTION FEATURES The XR17V3521 V352 is a single chip 2-channel PCI Express (PCIe) UART (Universal Asynchronous Receiver and Transmitter), optimized for higher performance and lower power. The V352 serves as a

silego

Abstract: TL1-12 SLG84401 932S401 CK410B CK410 SLG8
Contextual Info: SLG84401 High Performance Server & PCI Express Gen 2 Synthesizer Features • SRC output skew: < 250ps CK410B+ clock for Intel-based servers, PCI Express Gen 2 and QPI support. • ± 300ppm frequency accuracy on all outputs except • Supports spread spectrum modulation, 0 to 0.5% down

Contextual Info: PI2PCIE2442 PCI Express 2.0, 2-lane Exchange Switch Features Description • • • • • • • • Pericom Semiconductor’s PI2PCIE2442 is a differential exchange switch featuring pass-through pinout. It supports two full PCI Express lanes operating at 5.0Gbps PCIe® 2.0 performance.

AK8160B2

Contextual Info: [AK8160B2] AK8160B2 Low Power & Low Jitter Clock Generator for PCI Express 1. General Description The AK8160B2 is a member of AKM’s low power and low jitter clock generator family designed for PCI Express generation 2.0. This device has one PLL with spread spectrum SS function and enables to output

EIA-364-17

Abstract: EIA-364-65 mini pci express "mini PCI Express" EIA-364-70 EIA-364-9 EIA364-65 EIA-364-21 EIA-364-20 EIA-364-32
Contextual Info: Mini PCI Express Connector Product Specification 108-5899 10 OCT 05 Rev. C Mini PCI エクスプレス コネクタ Mini PCI Express Connector 1. 適用範囲 1.1 内容 本規格はMini PCI エクスプレス コネクタの製品性能 試験方法、品質保証の必要条件を規定している。

Contextual Info: PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Product Features Product Description • 14.318 MHz Crystal Input PI6C410 is a high-speed, low-noise clock generator designed to work with Intel Desktop PCI-Express Chipset. Spread Spectrum PLL based clock generator reduce EMI emission and support a wide range of frequencies.

CRYSTAL 14.318MHZ

Abstract: DOT96 PI6C410 PI6C410A PI6C410V PI6C410VE fsb -016 400000M kxo-01.1 20.0000mhz
Contextual Info: PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Product Features Product Description • 14.318 MHz Crystal Input PI6C410 is a high-speed, low-noise clock generator designed to work with Intel Desktop PCI-Express Chipset. Spread Spectrum PLL based clock generator reduce EMI emission and support a wide range of frequencies.

400M

Abstract: XIO2200 XIO2200A
Contextual Info: XIO2200A PCI Express to PCI Bus Translation Bridge with 1394a OHCI and Two-Port PHY Data Manual Literature Number: SCPS154B March 5 2007 Printed on Recycled Paper Contents Section 1 2 3 Page XIO2200 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contextual Info: XIO2000 PCI Express to PCI Bus Translation Bridge Data Manual Literature Number: SCPS097B November 2005 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

Contextual Info: XIO2000 PCI Express to PCI Bus Translation Bridge Data Manual Literature Number: SCPS097B November 2005 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

DS50PCI402

Abstract: PCIe cable pinout AN-1187 DS50PCI402SQE
Contextual Info: DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Transceiver with Equalization and De-Emphasis General Description Features The DS50PCI402 is a low power, 4 lane bidirectional buffer/ equalizer designed specifically for PCI Express Gen1 and Gen2 applications. The device performs both receive equalization and transmit de-emphasis, allowing maximum flexibility of physical placement within a system. The receiver is