PCI AHB DMA Search Results

PCI AHB DMA

Abstract: ahb slave RTL AMBA AHB bus AMBA AHB DMA DMA with AHB PCI AHB bridge
Contextual Info:  PCI specification 2.3 compliant  66MHz PCI performance  64-bit PCI data path PCI-M64AHB  Zero wait states burst mode  Full PCI bus master/target func- 64-bit/66MHz PCI PCI to AMBA AHB Interface Core tionality  Single PCI interrupt support

wishbone

Abstract: genesys virtex 5
Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

PCI AHB DMA

Abstract: tsmc 0.18 axi bridge
Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

Contextual Info: Compliant with PCI Express Base Specification 1.1 CPXP-EP PCI Express Endpoint Controller Megafunction with SoC Bridge Extensions for AHB, AXI and Wishbone Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It

circuit diagram of ddr ram

Abstract: sdram controller ip1010 PCI AHB DMA F00232
Contextual Info: Double Data Rate DDR SDRAM Controller (Pipelined Version) March 2004 IP Data Sheet • Bus Interfaces to PCI Target, PowerPC and AMBA (AHB) Buses Available ■ Complete Synchronous Implementation Features ■ Performance of Greater than 100MHz (200 DDR)

AMBA APB UART

Abstract: dlc10 UT699 352-CQFP state machine for ahb to apb bridge AMBA AHB memory controller UT699 memory map UT699 cpci driver ahb fsm SDRAM edac
Contextual Info: UT699 32-bit Fault-Tolerant LEON 3FT/SPARCTM V8 Processor Aeroflex Colorado Springs 800-645-8862 www.aeroflex.com/LEON August 2009 UT699 LEON 3FT Description T Operates from 3.3V for I/O and 2.5V for core T Multifunctional memory controller supports PROM, SRAM, SDRAM, and I/O

UT699

Abstract: leon3 UT699 DMA IEEE-1754 RAM EDAC SEU cpu aeroflex 512m pc133 SDRAM DIMM SDRAM edac IEEE754 UT699 memory map
Contextual Info: Standard Products UT699 LEON 3FT/SPARCTM V8 MicroProcessor Functional Manual August 23, 2010 www.aeroflex.com/LEON Table of Contents 1.0 INTRODUCTION 1.1 Scope 1.2 Architecture 1.3 Memory map 1.4 Interrupts 1.5 Signals 1.6 Clocking 1.6.1 Clock inputs 1.6.2 Clock gating

ahb slave to memory

Abstract: PCI AHB DMA
Contextual Info: Eureka Technology EP140 AHB Bus Slave Product Summary FEATURES • Supports AHB bus interface to the ARM CPU. • User interface designed for high speed access to two sets of on-chip or off-chip modules. • Four write buffers to process posted write. • Dual read buffers to process CPU read.

leon3

Abstract: UT699 UT699 cpci driver SJA1000 SpaceWire Packet Generator sparc v8 UT699 memory map IEEE754 SJA1000 mac 0x80000100
Contextual Info: Standard Products UT699 LEON 3FT/SPARCTM V8 MicroProcessor Advanced Users Manual March 2, 2009 www.aeroflex.com/LEON Table of Contents 1.0 INTRODUCTION 1.1 Scope 1.2 Architecture 1.3 Memory map 1.4 Interrupts 1.5 Signals 1.6 Clocking 1.6.1 Clock inputs 1.6.2 Clock gating

AMBA AHB specification

Abstract: AMBA AHB bus protocol PCI AHB bridge PCI AHB DMA inSilicon
Contextual Info: PCI Highlights 32-bit or 64-bit PCI bus path ♦ 32-bit or 64-bit application data path ♦ Zero Latency, Fast Backto-Back transfers PCI Parity Support for Memory Read Line/Multiple and Memory Write and Invalidate commands ♦ Dual Address cycles ♦ Loadable configuration

CQFP352

Abstract: CG484 CCGA484 Single Event Latchup ax2000 ECSS-E-ST-50-51C RTAX2000SL SpaceWire Standard Document ECSS-E-ST-50-12C RT3PE3000L SEU CCGA624 SpaceWire
Contextual Info: GAISLER Radiation-Tolerant 10x SpaceWire Router Radiation Tolerant 6x SpaceWire Router with PCI RT-SPW-ROUTER Data Sheet and User’s Manual Features • SpaceWire Router compliant with ECSS-E-ST-50-12C • Non-blocking switch-matrix connecting any input to any output

MRC D6 16A

Abstract: delta wireless doorbell B1565 transistor delta wireless doorbell IC 501 B1565 IXP400 b1566 IXP425 ldr t 9060 IXP422
Contextual Info: Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual September 2006 Order Number: 252480-006US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

PCI AHB DMA

Contextual Info: Reducing cost and time to market for SoC designs IBM CoreConnect and CPU support cores The embedded marketplace has a In addition, with each Power Design Kit, DMA to PLB4 controller long history of system-on-a-chip SoC IBM provides a bridge to the I/O core

Contextual Info: Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual June 2004 Document Number: 252480-004 Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Contents INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS

mips r4000

Contextual Info: QL902M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

Contextual Info: QL902M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

quicklogic an20

Abstract: 901M AA13 LVCMOS25 MIPS32 PC-100 QL901M R4000 Building An AMBA AHB Compliant Memory Controller
Contextual Info: QL901M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 133 MHz (173 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

32x32 Multiplier

Contextual Info: QL903M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

LVCMOS25

Abstract: MIPS32 PC-100 QL903M R4000 1024x32
Contextual Info: QL903M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

LVCMOS25

Abstract: MIPS32 PC-100 QL902M QL902M175 QL902M200 R4000 APB 630
Contextual Info: QL902M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 233 MHz (303 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

Contextual Info: QL901M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 133 MHz (173 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

LVCMOS25

Abstract: MIPS32 PC-100 QL903M R4000
Contextual Info: QL903M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 233 MHz (303 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

1024X3

Contextual Info: QL903M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz

Eclipse II Family

Contextual Info: QL902M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Ethernet Controllers CPU Core • Two 10/100 MACs • 32-bit MIPS 4Kc processor runs up to 200 MHz (260 Dhrystone MIPS) • 1.3 Dhrystone MIPS per MHz