PAGE MEMORY MANAGEMENT UNIT Search Results

irp 540

Abstract: AVR32113 AVR32
Contextual Info: AVR32113: Configuration and Use of the Memory Management Unit 32-bit Microcontrollers Features • • • • Translation lookaside buffers TLB Protected memory spaces Variable page size Uses exceptions for fast and easy management of TLB entries Application Note

Contextual Info: NSBMC096 NSBMC096 Burst Memory Controller Literature Number: SNOS687A NSBMC096-16 -25 -33 Burst Memory Controller General Description Features Y Y Interfaces directly to the i960 CA Integrated Page Cache Management Manages Page Mode Dynamic Memory devices

74fct861

Contextual Info: NSBMC096-16 -25 -33 Burst Memory Controller General Description Features Y Y Interfaces directly to the i960 CA Integrated Page Cache Management Manages Page Mode Dynamic Memory devices On-chip Memory Address Multiplexer Drivers Supports DRAMs trom 256 kB to 64 MB

MC88110

Abstract: motorola 88000 MC88100 MC88410 MC88110RC MC88200 M88000 mc88204rc 88000 stream register cache coherency
Contextual Info: The M88000 RISC Family In Brief . . . Page Architecture, Performance, and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . 2.3–2 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3–2 Cache/Memory Management Units . . . . . . . . . . . . . . . 2.3–3

Z8015

Contextual Info: Z8015 Z8000 PNNU Paged Memory Management Unit Product Specification A p r il 1985 • PMMU architecture supports m ultiprogram m ing systems and virtual memory implementations. ■ Dynamic page relocation makes software addresses independent of physical memory addresses.

SMARTCARD

Abstract: ST22FJ1M SMARTCARD IC datasheet A302 SMARTCARD IC
Contextual Info: ST22FJ1M 1 MByte Flash smartcard IC 32-bit platform smartcard IC 32-bit CPU Core Clock management Timer Peripherals SmartJTM Page Flash 256KB RAM 16KB Memory protection unit Power management Bus 1 RAM 16KB Unpredictable number generator Serial I/0 Interface

AN2794

Abstract: VA23 AN2795 AN2796 MPC603 MPC7450 MPC755 MPC8240 SR14 an2794 user manual
Contextual Info: Freescale Semiconductor Application Note Document Number: AN2794 Rev. 1, 08/2010 Page Table Translation Setup by Networking and Multimedia Group Freescale Semiconductor, Inc. Austin, TX This application note describes memory management unit MMU page table setup for classic Power

FFFC0003

Abstract: FFFC0006 SR14 SR15
Contextual Info: Memory Management Unit What you will learn Why have an MMU? Learn how to: • Initialize a BAT register • Set up the MMU for Page Translations - Invalidate TLBs - Define size and location of Hashed Page Table - Configure Segment registers for a task - Create the initial Hashed Page Table

CL1226

Abstract: Fujitsu SPARC
Contextual Info: F U JIT SU SPARC Memory Management Unit MB86920 FEATURES: • Compatible with the SPARC Reference MMU • Page level protections • 32-bit virtual address, 36-bit physical address • Selective flu shing and probing • Fixed 4K-byte page size • Hardware miss-processing

sck 084

Abstract: X25057 X5043
Contextual Info: Recommended System Management Alternative: X5043 X25057 4K 512 x 8 Bit 5MHz Low Power SPI Serial EEPROM with IDLock Memory DESCRIPTION • 5MHz clock rate • IDLock memory —IDLock first or last page, any 1/4 or lower 1/2 of EEPROM array • Low power CMOS

sck 084

Abstract: X25057 X25097 X5083
Contextual Info: Recommended System Management Alternative: X5083 X25097 8K 1024 x 8 Bit 5MHz Low Power SPI Serial EEPROM with IDLock Memory DESCRIPTION • 5MHz clock rate • IDLock memory —IDLock first or last page, any 1/4 or lower 1/2 of EEPROM array • Low power CMOS

79RC64575

Abstract: 79RC64574 RC32364 RC4640 RC4650 RC5000 RC64474 RC64575 5x1000 300-MFLOPS
Contextual Info: 79RC64574 79RC64575™ Advanced 64-bit Microprocessors Product Family Features Big- or Little-endian capability RC5000 compatible memory management – On-chip 48-entry, 96-page TLB, for advanced operating system support – Compatible with major operating systems:

MA2810

Abstract: idt79rc64t575 PQFP-128 footprint
Contextual Info: 79RC64574 79RC64575™ Advanced 64-bit Microprocessors Product Family Features Big- or Little-endian capability RC5000 compatible memory management – On-chip 48-entry, 96-page TLB, for advanced operating system support – Compatible with major operating systems:

MA2810

Abstract: 79RC64574 79RC64575 RC32364 RC4640 RC4650 RC5000 RC64474 RC64475 RC64575
Contextual Info: 79RC64574 79RC64575™ Advanced 64-bit Microprocessors Product Family HDWXUHV ◆ Big- or Little-endian capability RC5000 compatible memory management – On-chip 48-entry, 96-page TLB, for advanced operating system support – Compatible with major operating systems:

Contextual Info: Recommended System Management Alternative: X5083 X25097 8K 1024 x 8 Bit N O T FO R R EC N O EW M M D E ES N D IG E N D 5MHz Low Power SPI Serial EEPROM with IDLock Memory FEATURES DESCRIPTION • 5MHz clock rate • IDLock memory —IDLock first or last page, any 1/4 or lower 1/2 of

Contextual Info: Recommended System Management Alternative: X5043 X25057 4K 512 x 8 Bit N O T FO R R EC N O EW M M D E ES N D IG E N D 5MHz Low Power SPI Serial EEPROM with IDLock Memory FEATURES DESCRIPTION • 5MHz clock rate • IDLock memory —IDLock first or last page, any 1/4 or lower 1/2 of

PQFP-128 footprint

Abstract: RC32364 RC4640 RC4650 RC5000 RC64474 RC64475 RC64575 AXd 155 rc6414
Contextual Info: RC64574 RC64575™ Advanced 64-bit Microprocessors Product Family Preliminary Information*
  ◆ Big- or Little-endian capability RC5000 compatible memory management – On-chip 48-entry, 96-page TLB, for advanced operating system support – Compatible with major operating systems:

The PowerPC Microprocessor Family

Abstract: GP10 MPC823 partition translation lookaside buffer Instruction TLB Error Interrupt partition look-aside table
Contextual Info: SECTION 11 MEMORY MANAGEMENT UNIT The MPC823 implements a virtual memory management scheme that provides cache control, storage access protection, and effective-to-real address translation. This implementation includes separate instruction and data memory management units. The

8088 memory interface SRAM

Abstract: AMD Memory Management unit F0000-FFFFF D0000-D3FFF D0000-DFFFF function of internal code memory microcontroller isa bus interfacing with microprocessor 8088 SC310 B8000 A0000-FFFFF
Contextual Info: ÉlanTMSC300 and ÉlanSC310 Microcontrollers Memory Management Application Note The ÉlanTMSC300 and ÉlanSC310 microcontrollers contain a sophisticated memory management unit MMU , which makes PC/AT compatibility easy to achieve. However, if you wish to stray from

32-ENTRY

Abstract: MPC821 Instruction TLB Error Interrupt partition translation lookaside buffer
Contextual Info: SECTION 11 MEMORY MANAGEMENT UNIT 11.1 OVERVIEW The MPC821 implements a virtual memory management scheme that provides cache control, storage access protections, and effective to real address translation. The implementation includes separate instruction and data memory management units. The

32-ENTRY

Abstract: MPC860 Instruction TLB Error Interrupt
Contextual Info: SECTION 11 MEMORY MANAGEMENT UNIT 11.1 OVERVIEW The MPC860 implements a virtual memory management scheme that provides cache control, storage access protections, and effective to real address translation. The implementation includes separate instruction and data memory management units. The

PowerPC 750FX

Abstract: 750FX SR15 L2 ecc
Contextual Info:  IBM PowerPC 750FX RISC Microprocessor Technical Summary Version: 1.0 Preliminary May 30, 2002  Copyright and Disclaimer  Copyright International Business Machines Corporation 2002 All Rights Reserved Printed in the United States of America May 2002

PowerPC 750FX

Abstract: SA14-2766-02 750FX 750FL BA Series IBM MICROELECTRONICS tag 725 750FXTM
Contextual Info: Title Page IBM PowerPC 750FX and 750FL RISC Microprocessor User’s Manual SA14-2766-02 March 30, 2006 Copyright and Disclaimer Copyright International Business Machines Corporation 2003, 2006 All Rights Reserved Printed in the United States of America March 2006

Contextual Info: GEC PLESSEY S IM I ( \ I) ma3175i Memory Management Unit & Block Protect Unit I: (Advanced data) S10212ADF Issue 1.1 December 1990 Features Block Diagram M A 31751 • Radiation Hard CMOS/SOS Technology CPU B U SSES • User Configurable as Either a Memory