PAGE MEMORY MANAGEMENT UNIT Search Results

irp 540

Abstract: AVR32113 AVR32
Contextual Info: AVR32113: Configuration and Use of the Memory Management Unit 32-bit Microcontrollers Features • • • • Translation lookaside buffers TLB Protected memory spaces Variable page size Uses exceptions for fast and easy management of TLB entries Application Note

74fct861

Contextual Info: NSBMC096-16 -25 -33 Burst Memory Controller General Description Features Y Y Interfaces directly to the i960 CA Integrated Page Cache Management Manages Page Mode Dynamic Memory devices On-chip Memory Address Multiplexer Drivers Supports DRAMs trom 256 kB to 64 MB

MC88110

Abstract: motorola 88000 MC88100 MC88410 MC88110RC MC88200 M88000 mc88204rc 88000 stream register cache coherency
Contextual Info: The M88000 RISC Family In Brief . . . Page Architecture, Performance, and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . 2.3–2 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3–2 Cache/Memory Management Units . . . . . . . . . . . . . . . 2.3–3

SMARTCARD

Abstract: ST22FJ1M SMARTCARD IC datasheet A302 SMARTCARD IC
Contextual Info: ST22FJ1M 1 MByte Flash smartcard IC 32-bit platform smartcard IC 32-bit CPU Core Clock management Timer Peripherals SmartJTM Page Flash 256KB RAM 16KB Memory protection unit Power management Bus 1 RAM 16KB Unpredictable number generator Serial I/0 Interface

AN2794

Abstract: VA23 AN2795 AN2796 MPC603 MPC7450 MPC755 MPC8240 SR14 an2794 user manual
Contextual Info: Freescale Semiconductor Application Note Document Number: AN2794 Rev. 1, 08/2010 Page Table Translation Setup by Networking and Multimedia Group Freescale Semiconductor, Inc. Austin, TX This application note describes memory management unit MMU page table setup for classic Power

FFFC0003

Abstract: FFFC0006 SR14 SR15
Contextual Info: Memory Management Unit What you will learn Why have an MMU? Learn how to: • Initialize a BAT register • Set up the MMU for Page Translations - Invalidate TLBs - Define size and location of Hashed Page Table - Configure Segment registers for a task - Create the initial Hashed Page Table

sck 084

Abstract: X25057 X5043
Contextual Info: Recommended System Management Alternative: X5043 X25057 4K 512 x 8 Bit 5MHz Low Power SPI Serial EEPROM with IDLock Memory DESCRIPTION • 5MHz clock rate • IDLock memory —IDLock first or last page, any 1/4 or lower 1/2 of EEPROM array • Low power CMOS

sck 084

Abstract: X25057 X25097 X5083
Contextual Info: Recommended System Management Alternative: X5083 X25097 8K 1024 x 8 Bit 5MHz Low Power SPI Serial EEPROM with IDLock Memory DESCRIPTION • 5MHz clock rate • IDLock memory —IDLock first or last page, any 1/4 or lower 1/2 of EEPROM array • Low power CMOS

79RC64575

Abstract: 79RC64574 RC32364 RC4640 RC4650 RC5000 RC64474 RC64575 5x1000 300-MFLOPS
Contextual Info: 79RC64574 79RC64575™ Advanced 64-bit Microprocessors Product Family Features Big- or Little-endian capability RC5000 compatible memory management – On-chip 48-entry, 96-page TLB, for advanced operating system support – Compatible with major operating systems:

MA2810

Abstract: idt79rc64t575 PQFP-128 footprint
Contextual Info: 79RC64574 79RC64575™ Advanced 64-bit Microprocessors Product Family Features Big- or Little-endian capability RC5000 compatible memory management – On-chip 48-entry, 96-page TLB, for advanced operating system support – Compatible with major operating systems:

MA2810

Abstract: 79RC64574 79RC64575 RC32364 RC4640 RC4650 RC5000 RC64474 RC64475 RC64575
Contextual Info: 79RC64574 79RC64575™ Advanced 64-bit Microprocessors Product Family HDWXUHV ◆ Big- or Little-endian capability RC5000 compatible memory management – On-chip 48-entry, 96-page TLB, for advanced operating system support – Compatible with major operating systems:

zHM003

Abstract: RC32364 RC4640 RC4650 RC5000 RC64474 RC64475 RC64575 PQFP-128 footprint 0464c
Contextual Info: RC64574 RC64575™ Advanced 64-bit Microprocessors Product Family Preliminary Information* Featur tures ◆ Big- or Little-endian capability RC5000 compatible memory management – On-chip 48-entry, 96-page TLB, for advanced operating system support – Compatible with major operating systems:

PQFP-128 footprint

Abstract: RC32364 RC4640 RC4650 RC5000 RC64474 RC64475 RC64575 AXd 155 rc6414
Contextual Info: RC64574 RC64575™ Advanced 64-bit Microprocessors Product Family Preliminary Information*
  ◆ Big- or Little-endian capability RC5000 compatible memory management – On-chip 48-entry, 96-page TLB, for advanced operating system support – Compatible with major operating systems:

The PowerPC Microprocessor Family

Abstract: GP10 MPC823 partition translation lookaside buffer Instruction TLB Error Interrupt partition look-aside table
Contextual Info: SECTION 11 MEMORY MANAGEMENT UNIT The MPC823 implements a virtual memory management scheme that provides cache control, storage access protection, and effective-to-real address translation. This implementation includes separate instruction and data memory management units. The

32-ENTRY

Abstract: MPC821 Instruction TLB Error Interrupt partition translation lookaside buffer
Contextual Info: SECTION 11 MEMORY MANAGEMENT UNIT 11.1 OVERVIEW The MPC821 implements a virtual memory management scheme that provides cache control, storage access protections, and effective to real address translation. The implementation includes separate instruction and data memory management units. The

32-ENTRY

Abstract: MPC860 Instruction TLB Error Interrupt
Contextual Info: SECTION 11 MEMORY MANAGEMENT UNIT 11.1 OVERVIEW The MPC860 implements a virtual memory management scheme that provides cache control, storage access protections, and effective to real address translation. The implementation includes separate instruction and data memory management units. The

SMARTCARD

Abstract: A302 ST22FJ1M
Contextual Info: ST22FJ1M 1MB Flash smartcard IC 32-bit platform smartcard IC 32-bit CPU CORE Clock management Timer Peripherals SmartJTM Std Flash 768K RAM 16K Memory protection unit Power management Bug 1 RAM 16K Unpredictable number generator Serial I/0 Interface Bug 2

Contextual Info: GE C PLESSEY SEMI CONDS 43E GEC P LE SS EY D 37baS2S 00147bfl 1 IPLSB m a i ?504 MIL-STD-1750A Memory M anagement Unit/ Block Protect Unit S10208FDS Issue 1.3 O cto ber 1990 Features Block Diagram • Im plem ents Expanded Address and Block Protect Options of the MIL-STD-1750A Notice 1 Architecture

microcontroller ST92195

Abstract: ST92R195 ST92195 0x229F 56.OW11.3222C
Contextual Info: APPLICATION NOTE USING THE ST9+ MEMORY MANAGEMENT UNIT EXAMPLES FOR ST92195 AND ST92R195 by Microcontroller Division Applications INTRODUCTION This application note describes techniques for creating software applications using the Memory Management Unit (MMU) of the ST9+. In addition, it provides useful hints on using

37MB

Abstract: translation lookaside buffer tag
Contextual Info: TurboSPARC Microprocessor User's Manual Table of Contents 56k Chapter 1 - The TurboSPARC Microprocessor Includes: Integer Unit and Floating Point Controller, Floating Point Unit, Instruction Cache, Data Cache, Memory Management Unit, Bus Interface Unit. 330k Chapter 2 - TurboSPARC Architecture

BA1 U14

Abstract: ARM920T AT91RM9200 ISO7816 AT91RM9200 SDRAM
Contextual Info: Features • Incorporates the ARM920T ARM Thumb® Processor • • • • • • • • • • • • – 200 MIPS at 180 MHz, Memory Management Unit – 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer – In-circuit Emulator including Debug Communication Channel

eeprom 25080

Abstract: watch dog schema transmitters schema TV TRANSMITTER PROJECT Microcontroller AT89C2051 virtual machine 88CFX4000P 88CFX4002P TS102 1408-bit
Contextual Info: Security & Chip Card ICs SLE 88CFX4002P 32-Bit Multi Application Security Controller with powerful Memory Management & Protection Unit in 0.13µm CMOS Technology, 240 Kbytes ROM, 400 Kbytes configurable EEPROM, 16 Kbytes RAM, and 1408-bit Crypto Engine Crypto@1408Bit

eeprom 25080

Abstract: 25080 eeprom watch dog schema CFX4 Microcontroller AT89C2051 virtual machine timer schema AIS-31 schema eeprom tv TV TRANSMITTER PROJECT 88CFX4000P
Contextual Info: Security & Chip Card ICs SLE 88CFX4000P 32-Bit Multi Application Security Controller with powerful Memory Management & Protection Unit in 0.13µm CMOS Technology, 400 Kbytes configurable EEPROM, 16 Kbytes RAM, and 1408-bit Crypto Engine Crypto@1408Bit Preliminary Short Product Information 04.03

HD6417729RBP167B

Abstract: HD6417729RF167B HD6417729RHF200B SH7729 SH7729R 32-bit microprocessor pipeline architecture
Contextual Info: Section 1 Overview 1.1 Features The SH7729R is a single-chip RISC microprocessor that integrates a 32-bit RISC-type SuperH RISC engine architecture CPU with a digital signal processing DSP extension as its core, together with cache memory, an on-chip X/Y memory, and a memory management unit (MMU),