PACKAGE OUTLINE WEIGHT Search Results

F2B transistor

Abstract: 3p transistor transistor TO-3P Outline Dimensions transistor 975 transistor 545
Contextual Info: Transistor Outline Package TO-3P LH Package Outline Dimensions Outline Dimensions Unit: mm 20.5 max 1.0 +0.3 –0.25 26.0 ±0.5 2.0 1.5 3.0 20.0 ±0.6 2.5 2.5 1.5 11.0 2.0 4.0 6.0 φ3.3 ±0.2 1 (Bottom view) Toshiba package name Toshiba package code Notes

nec 44 pin LQFP

Abstract: BGA and QFP Package 256-pin BGA drawing 14 pin ic 28-pin QFP nec 44-pin qfp 44-Pin QFN 65A1 nec 44-pin LQFP ic packages
Contextual Info: CHAPTER 3 SURFACE MOUNT PACKAGES 3.1 LINEUP OF SURFACE MOUNT IC PACKAGES 3.2 LIST OF SURFACE MOUNT IC PACKAGES 1 Plastic SOP (Small Outline Package) (2) Ceramic WSOP (Small Outline Package with Window) (3) Plastic shrink SOP (Shrink Small Outline Package)

toshiba mosfet

Abstract: jeita To-126 transistor to6 trangister TO126 package
Contextual Info: Trangister Outline Package TO-126 Package Outline Dimensions Outline Dimensions Unit: mm 8.3 max 11.0 ±0.3 3.5 φ3.1 ±0.1 1.9 max 0.75 ±0.15 2.3 ±0.1 2 3 0.75 ±0.15 3.4 max 1 1.6 2.3 ±0.1 14.0 min 1.9 max 1.0 max Toshiba package name Toshiba package code

TO-3P Jedec package outline

Abstract: 3p transistor transistor outline package 3
Contextual Info: Transistor Outline Package TO-3P W Package Outline Dimensions Outline Dimensions Unit: mm 0.8 +0.2 –0.1 15.5 ±0.3 A 20.0 ±0.3 3.0 max 4.5 φ3.2 ±0.2 A 1.0 +0.3 –0.25 5.45 1 2 3 3 0.8 +0.3 –0.1 5.45 1 (Bottom view) Toshiba package name Toshiba package code

transistor TO-3P Outline Dimensions

Abstract: TRANSISTOR 545 3p transistor TO-3P Jedec package outline TOSHIBA IGBT DATA BOOK
Contextual Info: Transistor Outline Package TO-3P L Package Outline Dimensions Outline Dimensions Unit: mm 20.5 max 26.0 ±0.5 11.0 2.0 4.0 6.0 φ3.3 ±0.2 3.0 1.0 +0.3 –0.25 20.0 ±0.6 2.5 2.5 3 1 (Bottom view) Toshiba package name Toshiba package code Notes • The above diagrams may not be actual sizes. Diagrams may be enlarged,

transistor TO-220 Outline Dimensions

Contextual Info: Transistor Outline Package TO-220 W Package Outline Dimensions Outline Dimensions Unit: mm 10.0 ±0.3 A 9.0 3.2 2.8 φ3.65 ±0.2 0.6 ±0.1 15.0 ±0.3 9.5 ±0.2 0.75 ±0.25 0.62 ±0.15 2.54 12.8 ±0.5 A 1 2 3 3 0.57 +0.25 –0.10 2.54 1 (Bottom view) Toshiba package name

Contextual Info: Transistor Outline Package TO-220SIS Package Outline Dimensions Outline Dimensions Unit: mm 2.7 ±0.2 10.0 ±0.3 A 15.0 ±0.3 3.9 3.0 φ3.2 ±0.2 0.69 ±0.15 2.54 13.0 ±0.5 A 2.54 1 2 3 0.64 ±0.15 4.5 ±0.2 M 2.6 ±0.1 φ0.2 2.8 max 1.14 ±0.15 Toshiba package name

TRANSISTOR S1A

Abstract: TO220FL TOSHIBA IGBT DATA BOOK
Contextual Info: Transistor Outline Package TO-220FL Package Outline Dimensions Outline Dimensions Unit: mm 1.32 10.6 max 9.1 10.3 max 2.5 max 0.76 2.54 ±0.25 12.6 min 1.6 max 2.54 ±0.25 3 0.5 2 1 1 2 3 4.7 max 2.6 Bottom view Toshiba package name TO–220FL Diode 12–10D1A

TOSHIBA IGBT DATA BOOK

Abstract: TO-220AB transistor package 10P1A
Contextual Info: Transistor Outline Package TO-220AB Package Outline Dimensions Outline Dimensions Unit: mm 1.32 15.7 max 3.0 φ3.6 ±0.2 6.7 max 10.3 max 2.5 max 12.6 min 1.6 max 0.76 3 2 3 0.5 1 Bottom view Toshiba package name Toshiba package code Notes • The above diagrams may not be actual sizes. Diagrams may be enlarged,

Contextual Info: Transistor Outline Package Center Leadless Type TO–220NIS (Center Leadless Type) Package Outline Dimensions Outline Dimensions Unit: mm 2.7 ±0.2 10.0 ±0.3 5.6 max 1.1 0.75 ±0.15 15.0 ±0.3 Notes • The above diagrams may not be actual sizes. Diagrams may be enlarged,

sop package tray

Abstract: 29754* intel weight of SOP package SOP JEDEC tray
Contextual Info: SMALL OUTLINE PACKAGE GUIDE OVERVIEW Intent This overview provides a quick reference for the Small Outline Package Guide, Intel literature order number 296514. Contents The table below details, in outline form, the type of information that can be found in the guide.

SSOP42-P-450-0

Contextual Info: APPENDIX 3.9 Package outline 3.9 Package outline 42P2R-A Plastic 42pin 450mil SSOP EIAJ Package Code SSOP42-P-450-0.80 Weight g 0.63 JEDEC Code – Lead Material Alloy 42/Cu Alloy e b2 22 Caution ! E HE e1 I2 42 F Symbol TBD 21 1 A D Recommended Mount Pad

TOSHIBA IGBT DATA BOOK

Abstract: transistor R1A r1a transistor 10R1A 10R1B 2-10R1A
Contextual Info: Transistor Outline Package New Isolated Type TO–220NIS Package Outline Dimensions Outline Dimensions Unit: mm 2.7 ±0.2 10.0 ±0.3 5.6 max 1.1 1.1 0.75 ±0.15 2.54 ±0.25 15.0 ±0.3 13.0 min 3.9 3.0 φ3.2 ±0.2 2 3 0.75 ±0.15 4.5 ±0.2 1 2.6 2.54 ±0.25

transistor t1A

Abstract: t1a transistor toshiba mosfet
Contextual Info: Taped Power Device Large Package TPL Package Outline Dimensions Outline Dimensions Unit: mm 10.0 ±0.2 13.4 ±0.2 φ1.2 1.5 1.4 14.8 ±0.5 0.5 +0.15 –0.05 2.5 0.5 +0.15 –0.05 1 2 4.5 ±0.2 2 2.5 3 Toshiba package name Toshiba package code 2–10T1A MOSFET

SOP20 Package

Abstract: SOP20 20 pin Package PSOP-20
Contextual Info: 20-Pin Small Outline Package SOP20 Package Outline Dimensions Outline Dimensions 1.27 0.43 +0.07 –0.04 0 ～10゜ 0.8 ±0.2 0.25 M 13.3 max 0.1 Land Pattern Example Enlarged view of A A 0.1 +0.1 –0.05 1.5 ±0.2 12.8 ±0.2 1.9 max 0.685 typ. 0.25 10 +0.075

SSOP24

Abstract: land pattern ssop24
Contextual Info: 24-Pin Shrink Small Outline Package SSOP24 Package Outline Dimensions Outline Dimensions Unit: mm 0.25 7.6 ±0.3 +0.03 0.15 -0.01 13 5.6 ±0.2 24 0 ～10゜ 0.45 ±0.2 0.325 typ. 0.65 12 0.22 +0.09 –0.06 0.1 Land Pattern Example 0.13 M Enlarged view of A

land pattern for TSSOP-8

Abstract: land pattern for TSSOP land pattern for TSsOP 8 TSSOP8 Package
Contextual Info: 8-pin Thin Shrink Small Outline Package TSSOP-8 Package Outline Dimensions Outline Dimensions Unit: mm 0.25 ±0.05 4 0.6 ±0.2 0.85 ±0.05 0.65 0.65 3.3 max 3.0 ±0.1 0.05 Land Pattern Example 0.16 +0.04 –0.02 0.65 0.05 ±0.05 1 0.525 6.4 ±0.3 5 4.4 ±0.1

SOP16 Package

Abstract: sop16
Contextual Info: 16-Pin Small Outline Package SOP16 Package Outline Dimensions Outline Dimensions Unit: mm 1.27 8 0.43 +0.07 –0.04 10.8 max 0.1 Land Pattern Example 0.25 +0.075 0 ～10゜ 0.8 ±0.2 0.25 M Enlarged view of A A 0.1 +0.1 –0.05 1.5 ±0.2 10.3 ±0.2 1.9 max

3p transistor

Abstract: TO-3P Jedec package outline
Contextual Info: Transistor Outline Package New Isolated Type TO–3P (N) IS Package Outline Dimensions Outline Dimensions Unit: mm 3.5 15.8 ±0.5 3.6 max 2.0 1.0 +0.25 –0.15 5.45 ±0.2 21.0 ±0.5 19.4 min (15.5) 5.5 φ3.6 ±0.2 0.6 +0.25 –0.15 2 3 5.0 ±0.3 1 3.15 +0.2

W1A 95 3 pin transistor

Abstract: transistor W1A W1A 95 TO220SM
Contextual Info: Transistor Outline Package TO-220SM W Package Outline Dimensions Outline Dimensions Unit: mm 10.0 ±0.3 0.4 ±0.1 2.35 ±0.1 6.8 10.0 ±0.3 1.1 2.54 ±0.25 0.4 ±0.1 2 3 Land Pattern Example 3 2 1 (Bottom view) 0.1 ±0.1 3.5 ±0.2 2.76 2.34 ±0.25 1 8.0

QFP64-P-1414-0

Abstract: SDIP64-P-750-1 3804 f
Contextual Info: APPENDIX 3.6 Package outline 3.6 Package outline 64P6N-A Plastic 64pin 14✕14mm body QFP EIAJ Package Code QFP64-P-1414-0.80 Weight g 1.11 Lead Material Alloy 42 MD e JEDEC Code – HD 64 b2 ME D 49 1 I2 48 Recommended Mount Pad HE E Symbol 33 16 A 32 L1

QFP64-P-1414-0

Abstract: SDIP64-P-750-1
Contextual Info: APPENDIX 3.6 Package outline 3.6 Package outline 64P6N-A Plastic 64pin 14✕14mm body QFP EIAJ Package Code QFP64-P-1414-0.80 Weight g 1.11 Lead Material Alloy 42 MD e JEDEC Code – HD 49 b2 64 ME D 1 48 I2 HE E Recommended Mount Pad Symbol A A1 A2 b c D

3p transistor

Abstract: 2-16C1B
Contextual Info: Transistor Outline Package New Type TO–3P (N) Package Outline Dimensions Outline Dimensions Unit: mm 1.8 max 15.9 max 3.3 max 2.0 ±0.3 1.0 +0.3 –0.25 5.45 ±0.2 20.5 ±0.5 9.0 2.0 20.0 ±0.3 4.5 φ3.2 ±0.2 3 4.8 max 2 2.8 1 (Bottom view) 0.6 +0.3 –0.1

tssop14 0.65 land pattern

Abstract: TSSOP14 package TSSOP14
Contextual Info: 14-Pin Thin Shrink Small Outline Package TSSOP14 Package Outline Dimensions Outline Dimensions Unit: mm 0.25 +0.03 6.4 ±0.2 4.4 ±0.1 0.15 -0.01 8 14 0 ～10゜ 1 7 0.22 +0.09 –0.06 0.55 typ. 0.5 0.45 ～ 0.75 0.13 M 0.65 S 0.1 S Land Pattern Example