PA7572P-20 Search Results
PA7572P-20 Datasheets (4)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| PA7572P-20 |
|
4.5 to 5.5 V, speed 20=13 ns/20 ns tpd/tpdx programmable electrically erasable logic array | Original | 245.79KB | 10 | ||
| PA7572P-20 |
|
PEEL Array Programmable Electrically Erasable Logic Array | Original | 326.64KB | 10 | ||
| PA7572P-20 | Integrated Circuit Technology | CPLD, PA7572 Family, EECMOS Process, 72 Macro Cells, 60 Reg., 24 User I/Os, 5V Supply, 20 Speed Grade, 40DIP | Original | 203.89KB | 10 | ||
| PA7572P-20L |
|
PEEL Array Programmable Electrically Erasable Logic Array | Original | 326.64KB | 10 |