PA7572P-20 |
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Anachip
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4.5 to 5.5 V, speed 20=13 ns/20 ns tpd/tpdx programmable electrically erasable logic array |
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Original |
PDF
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PA7572P-20 |
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Anachip
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PEEL Array Programmable Electrically Erasable Logic Array |
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Original |
PDF
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PA7572P-20 |
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Integrated Circuit Technology
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CPLD, PA7572 Family, EECMOS Process, 72 Macro Cells, 60 Reg., 24 User I/Os, 5V Supply, 20 Speed Grade, 40DIP |
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Original |
PDF
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PA7572P-20L |
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Anachip
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PEEL Array Programmable Electrically Erasable Logic Array |
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Original |
PDF
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PA7572PI-20 |
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Anachip
|
4.5 to 5.5 V, speed 20=13 ns/20 ns tpd/tpdx programmable electrically erasable logic array |
|
Original |
PDF
|
PA7572PI-20 |
|
Anachip
|
PEEL Array Programmable Electrically Erasable Logic Array |
|
Original |
PDF
|
PA7572PI-20 |
|
Integrated Circuit Technology
|
CPLD, PA7572 Family, EECMOS Process, 72 Macro Cells, 60 Reg., 24 User I/Os, 5V Supply, 20 Speed Grade, 40DIP |
|
Original |
PDF
|
PA7572PI-20L |
|
Anachip
|
PEEL Array Programmable Electrically Erasable Logic Array |
|
Original |
PDF
|