P181 G Search Results

S-CPGA-P181

Contextual Info: MECHANICAL DATA MCPG020 – NOVEMBER 1995 GE S-CPGA-P181 CERAMIC PIN GRID ARRAY 1.590 (40,40) SQ 1.148 (37,60) 1.400 (35,56) TYP 0.100 (2,54) TYP R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.185 (4,70) 0.140 (3,55) 0.060 (1,52) 0.040 (1,02)

smd P181

Abstract: p181 smd P181 G IQXO-70 IQXO-70I IQXO-71 IQXO-71I 4.0MHZ IQXO-71I
Contextual Info: IQXO-70, -71 Outline in mm inches - (scale 2:1) ISSUE 7; 13 SEPTEMBER 1999 Delivery Options n 5 .0 (0 .1 9 7 ) Common frequencies are available from stock please see p181 for details n Tri-state HCMOS/TTL (5.0V)(IQXO-70) n Tri-state HCMOS (3.3V) (IQXO-71)

Contextual Info: MECHANICAL DATA MCPG014 – OCTOBER 1995 GB S-CPGA-P181 CERAMIC PIN GRID ARRAY 1.590 (40,40) SQ 1.148 (37,60) 1.400 (35,56) TYP 0.100 (2,54) TYP R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.185 (4,70) 0.140 (3,55) 0.055 (1,40) 0.045 (1,14)

p181 gb

Abstract: S-CPGA-P181 p181 P181 pdf datasheet
Contextual Info: MECHANICAL DATA MCPG014 – OCTOBER 1995 GB S-CPGA-P181 CERAMIC PIN GRID ARRAY 1.590 (40,40) SQ 1.148 (37,60) 1.400 (35,56) TYP 0.100 (2,54) TYP R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.185 (4,70) 0.140 (3,55) 0.055 (1,40) 0.045 (1,14)

P181 G

Contextual Info: 3 /1 6 4 .8 m m SNAP-IN PANEL MOUNT LEDs COLOR CODE LEGEND PART NUMBER SELECTION GUIDE OPTIONS SERIES LENS - 1 |- BRIGHTNESS CHARACTERISTICS COLOR -CODE (SEE LEGEND) - ELECTRICAL CHARACTERISTICS COLOR CODE ELECTRICAL CHARACTERISTICS TR5 TY5

J29 P190

Abstract: L-29 p302 transistor p98 p115 p106 P191 transistor be p88 P142 P143
Contextual Info: XC4000XLA/XV Field Programmable Gate Arrays January 28, 1999 Version 1.0 0* R XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table

Contextual Info: Product Obsolete/Under Obsolescence R XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table Continued XC4013XLA Pinout Table PAD NAME PQ160 PQ208 PQ240 I/O – – P21 BG256 H1 PAD NAME PQ160 PQ208

J29 P190

Abstract: AG29 p115 p106 transistor be p88 XC4028XLA P142 P143 P144 P145
Contextual Info: XC4000XLA/XV Field Programmable Gate Arrays January 28, 1999 Version 1.0 0* R XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table

t4 p131

Abstract: P118-P119 P181 p135 P28 E8 P-197 P143 P144 p147 PQ160
Contextual Info: XC4013 and XC4013E Pinout Table Pin Name VCC I/O A8 I/O(A9) I/O I/O I/O I/O I/O(A10) I/O(A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O(A12) I/O(A13) I/O I/O I/O I/O I/O(A14) SGCK1(A15;I/O) VCC GND PGCK1(A16;I/O) I/O(A17) I/O I/O I/O(TDI) I/O(TCK) I/O I/O

P239

Abstract: P181 P185 P-239 P212 P213 p178 P215 P216 P218
Contextual Info: XC4025 and XC4025E Pinout Table Pin Name VCC I/O A8 I/O(A9) I/O I/O I/O I/O I/O(A10) I/O(A11) I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O(A12) I/O(A13) I/O I/O I/O I/O I/O I/O I/O(A14) SGCK1(A15;I/O) VCC GND PGCK1(A16;I/O) I/O(A17)

J29 P190

Abstract: p239 P116 Diode XC4028XLT XC4062XLT XC4013XLT diode P113 DIODE AJ22 AK19 diode P181
Contextual Info: XC4000XLT Family Field Programmable Gate Arrays  December 10, 1997 Version 0.8 4* Advance Product Specification XC4000XLT Features XC4000XLT Electrical Features Note: This data sheet describes the XC4000XLT Family devices. This information does not necessarily apply to the

i440

Abstract: C783 BP107 C783CS SCR 500A
Contextual Info: MMEREX C783 Powerex, Inc., 200 HiUis Street, Youngwood, Pennsylvania 15697-1800 412 925-7272 PhâSG Powerex, Europe, S.A. 428 Avenue G. Durand, BP107, 72003 Le Mans, France (43) 41.14.14 4 onn . C O fltT O l S C R . 1800 Amperes Average 3700 Volts C783 Phase Control SCR

n4 p69

Abstract: v1 j p304 MQ240 P212 P213 P214 P215 PG223 XC4025 XC4025E
Contextual Info: Xilinx Common Package Footprints BG225 225-Pin Ball Grid Array XC4010BG225 (Bottom View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VCC PGCK2 (I/O) I/O I/O I/O I/O I/O VCC I/O N.C. I/O I/O I/O I/O VCC P SGCK2 (I/O) M0 I/O (HDC) I/O (LDC) N.C. I/O N.C. I/O (/INIT)

AF2.5 din 74

Abstract: P181 Japan K2808 634 p181 715 P181 K1805 J29 P190 xc4005e-TQ144 499 P44 20 g8 p281
Contextual Info: XC4000E and XC4000X Series Field Programmable Gate Arrays November 10, 1997 Version 1.4 4 Device-Specific Pinout Tables Device-specific tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locations around the die, and include boundary scan register locations.

PJ87

Abstract: diode pj87 diode p115 P116 Diode P119H DIODE AH10 DIODE AJ15 J29 P190 P128J
Contextual Info: £ XILINX XC4000XLT Family Field Programmable Gate Arrays December 10, 1997 Version 0.8 Advance Product Specification XC4000XLT Features XC4000XLT Electrical Features Note: This data sheet describes the XC4000XLT Family devices. This information does not necessarily apply to the

MOSFET P239

Abstract: XC4000XLA VDR P275 L20 P55 MOSFET XC4000E XC4000X XC4000XL XC4000XV XC4013XLA XC4028XLA
Contextual Info: XC4000XLA/XV Field Programmable Gate Arrays R February 1, 1999 Version 1.0 6* Product Specification XC4000XLA/XV Family FPGAs XC4000XLA/XV Electrical Features Note: XC4000XLA devices are improved versions of XC4000XL devices. The XC4000XV devices have the

J29 P190

Abstract: p331 TRANSISTOR p477 p525 P364 P521 G P440 C 05 P521 G2 p372 transistor P519
Contextual Info: MSX Family Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor

11AK12

Abstract: 4062XLA Trans Metrics P100 4044XL AD 690 xilinx HQ240 diode ak14
Contextual Info: £ X IU N X XC4000XLA/XV Field Programmable Gate Arrays February 1, 1999 Version 1.0 Product Specification XC4000XLA/XV Family FPGAs XC4000XLA/XV Electrical Features Note: XC 4000XLA devices are improved versions of X C 4000X L devices. The XC4000X V devices have the

p181 g8

Abstract: 105 p180 g8 707 p181 g5209 p115 SPARTAN XC2S50 SPARTAN-II xc2s200 pq208 tms 374 transistor be p88 P140
Contextual Info: Spartan-II 2.5V FPGA Family: Pinout Tables R DS001-4 v2.4 April 30, 2001 Preliminary Product Specification Pin Definitions Pin Name Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 No Input Clock input pins that connect to Global Clock Buffers. These pins become

transistor P397

Abstract: P521 G P089 P521 FAIRCHILD transistor P479 MSX532 MSX532TB792 P039 UP501 P449
Contextual Info: Revised June 2002 MSX532 532 Port Digital Crosspoint Switch with LVTTL I/O’s General Description Features The MSX family of SRAM-based bit-oriented switching devices offer flow-through NRZ data rates of up to 150Mb/s and registered clock frequencies of up to 75MHz. The I/O

P153 transistor

Contextual Info: FLAT PANEL TYPE MULTIANODE PHOTOMULTIPLIER TUBE ASSEMBLY H9500, H9500-03 52 mm Square, Bialkali Photocathode, 12-stage, 16 x 16 Multianode, Small Dead Space, Fast Time Response FEATURES ●Small Animal Imaging ●Compact Gamma Camera ●Scinti-mammography

IDT72401

Abstract: IDT72402 IDT72403 IDT72404
Contextual Info: IDT72401 IDT72402 IDT72403 IDT72404 CMOS PARALLEL FIFO 64 x 4 and 64 x 5 Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • • • • • • • First-ln/First-Out Dual-Port memory 64 x 4 organization IDT72401/72403

ptc j29 p190

Abstract: elex 15101 datasheet str 5707 intel 865 MOTHERBOARD pcb CIRCUIT diagram str 5707 pci pcb layout vhdl code for 8-bit parity generator XCS40PQ208 machine maintenance checklist CD 5888
Contextual Info: Xilinx PCI the CORE of a GREAT IDEA The Programmable Logic CompanySM Printed in U.S.A. Data Book 2100 Logic Drive San Jose, CA 95124-3400 Tel: 1-408-559-7778 Fax: 1-408-559-7114 e-mail: hotline@xilinx.com web: www.xilinx.com PN 0401764 5/98 Xilinx PCI The

Contextual Info: IDT72401 IDT72402 IDT72403 IDT72404 CMOS PARALLEL FIFO 64 x 4 and 64 x 5 IDT72404 are asynchronous high-performance First-ln/First-Out memories organized as 64 words by 5 bits. The IDT72403 and IDT72404 also have an Output Enable OE pin. The FlFOs accept 4-bit or 5-bit data at the data input