OSAM MARKING CODE Search Results

4413

Abstract: IDT77155 IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 osam marking code
Contextual Info: SECTION 2 IDT77V400 Switching Memory 2.1 IDT77V400 Switching Memory Description The IDT77V400 Switching Memory is designed to provide essential data path functionality for switches, concentrators and expanders in Asynchronous Transfer Mode ATM Networks. The IDT77V400 supports aggregate data throughput at rates up to 1.24 Gbps and has 8192

b1416

Abstract: D1416 b14-16 IDT77155 IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640
Contextual Info: IDT77V400 SwitchStarTM ATM Cell Based 8 x 8 1.2Gbps non-blocking Integrated Switching Memory
Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can
  
Single chip supports an 8 x 8 port switch at 155Mbps per be independently chosen for Input and Output ports

IOD17

Abstract: IOD16 IOD22 3606
Contextual Info: IDT77V400 SwitchStarTM ATM Cell Based 8 x 8 1.2Gbps non-blocking Integrated Switching Memory
Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can
  
Single chip supports an 8 x 8 port switch at 155Mbps per be independently chosen for Input and Output ports

IDT77155

Abstract: IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 3606
Contextual Info: SWITCHStARTM ATM CELL BASED 8 X 8 PRELIMINARY 1.24Gbps NON-BLOCKING IDT77V400 INTEGRATED SWITCHING MEMORY Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip supports an 8 x 8 port switch at 155Mbps per port Fusion MemoryTM technology utilized to provide the

IDT77V400

Abstract: IDT77V500 IDT77V550 IOD-11 D14-16 3606
Contextual Info: IDT77V400 SwitchStarTM ATM Cell Based 8 x 8 1.2Gbps non-blocking Integrated Switching Memory Features List ! Single chip supports an 8 x 8 port switch at 155Mbps per port ! Central Memory Architecture eliminates Head-of-Line Blocking by sharing the memory array with all ports

B1416

Abstract: E1113 1CS MARKING IDT77V400 IDT77V500 IDT77V550 13-bitcell m1416 s156 A1516
Contextual Info: IDT77V400 SwitchStarTM ATM Cell Based 8 x 8 1.2Gbps non-blocking Integrated Switching Memory Features List ! Single chip supports an 8 x 8 port switch at 155Mbps per port ! Central Memory Architecture eliminates Head-of-Line Blocking by sharing the memory array with all ports

body marking MCL

Abstract: IDT77155 IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 PN100-1 osam marking code
Contextual Info: SWITCHStARTM PRELIMINARY ATM CELL BASED IDT77V500 1.24Gbps NON-BLOCKING INTEGRATED SWITCH CONTROLLER Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip controller for IDT77V400 Switching Memory One IDT77V500 and one IDT77V400 form the core required

BC-144-1

Abstract: IDT77V400 IDT77V500
Contextual Info: IDT77V500 SwitchStarTM ATM Cell Based 1.2Gbps non-blocking Integrated Switch Controller
  ◆ One IDT77V500 can manage up to eight IDT77V400's without derating for larger switch configurations Industrial temperature range -40° C to +85° C is available

IDT77V550

Abstract: PN100-11 IDT77V400 IDT77V500
Contextual Info: IDT77V500 SwitchStarTM ATM Cell Based 1.2Gbps non-blocking Integrated Switch Controller Features ◆ Single chip controller for IDT77V400 Switching Memory One IDT77V500 and one IDT77V400 form the core required for a 1.2Gbps 8 x 8 port non-blocking switch ◆ Supports up to 8192 Virtual Connections VCs

IDT77V400

Abstract: IDT77V500 IDT77V550 PN100-11
Contextual Info: IDT77V500 SwitchStarTM ATM Cell Based 1.2Gbps non-blocking Integrated Switch Controller Features ◆ Single chip controller for IDT77V400 Switching Memory One IDT77V500 and one IDT77V400 form the core required for a 1.2Gbps 8 x 8 port non-blocking switch ◆ Supports up to 8192 Virtual Connections VCs

Contextual Info: SWITCHStAR PRELIMINARY ATM CELL BASED IDT77V500 1.24Gbps NON-BLOCKING INTEGRATED SWITCH CONTROLLER \ * 'fcfcM S’* v \. Features * Single chip controller for IDT77V400 Switching Memory * One IDT77V500 and one IDT77V400 form the core required for a 1.24Gbps 8 x 8 port non-blocking switch

SRT9

Abstract: osam marking code 4258A MT43C MT43C425
Contextual Info: PRELIMINARY l^ iic n o N 256K X MT43C 4257A/8A 4 T R IP LE -P O R T DRAM FEATURES • • • • • • • • • • • • • PIN ASSIGNMENT Top View Three asynchronous, independent, data-access ports Fast access times: 70ns random, 22ns serial Operation and control compatible w ith 1 Meg VRAM

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