ORP 112 Search Results

LSC 132

Abstract: 3256E
Contextual Info: ispLSI and pLSI 3256E ® High Density Programmable Logic OR Array A2 A3 B1 D Q F2 D Q F1 Twin GLB F0 D Q E3 D Q E2 D Q B2 E1 Global Routing Pool B3 E0 C0 C1 ORP C2 C3 ORP ORP Boundary Scan F3 D Q Array G0 D Q D Q OR B0 ORP G1 D0 D1 ORP D2 ORP A1 G2 ORP

B272

Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

B272

Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

203d6

Abstract: B272
Contextual Info: ispLSI 3160 Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay

B272

Abstract: BC470
Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

100LQ128

Abstract: 2096E 2096E180LT
Contextual Info: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) C7 C5 C4 Output Routing Pool (ORP) C3 C2 C1 C0 A0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool

2096E

Contextual Info: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) C7 C5 C4 Output Routing Pool (ORP) C3 C2 C1 C0 A0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool

2096E

Contextual Info: ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) C7 C5 C4 Output Routing Pool (ORP) C3 C2 C1 C0 A0 B7 D Q A1 A2 GLB Logic Array B6 D Q Global Routing Pool

lM 3160

Contextual Info: ispLSI and pLSI 3160 ® High Density Programmable Logic Features Functional Block Diagram E3 E2 E1 E0 A0 ORP OR Array ORP A2 A3 D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

B272

Abstract: 203d6
Contextual Info: ispLSI 3160 High Density Programmable Logic Features Functional Block Diagram E3 E2 E1 E0 A0 ORP OR Array ORP A2 A3 D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay

Contextual Info: ispLSI 3160 High Density Programmable Logic Features Functional Block Diagram E3 E2 E1 E0 A0 ORP OR Array ORP A2 A3 D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay

4512c

Abstract: ispMACH lc4064v LC4032 LC4032V-10TN48I 4032V 4000ZC LC4384V-35TN176C LC4512V-5FN256I LC4128V-5T128C LC4512V
Contextual Info: Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 16 16 Generic Logic Block 36 I/O Block ORP 16 36 16 16 36 36 Generic 16 Logic Block VCCO1 GND TCK TMS TDI TDO VCC GND GOE0 GOE1 16 I/O Bank 0 ORP Generic Logic Block I/O Block ORP I/O Bank 1 I/O Block

2096-100LT

Contextual Info: ispLSI 2096/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS Output Routing Pool ORP Output Routing Pool (ORP) C7 • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 4000 PLD Gates 96 I/O Pins, Six Dedicated Inputs

2128-80LT

Contextual Info: ® ispLSI and pLSI 2128 High-Density Programmable Logic Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) D7 D3 D5 fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable

lattice 1996

Contextual Info: ispLSI and pLSI 2128 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) D7 D3 D5 fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable

3256E

Contextual Info: ispLSI 3256E High Density Programmable Logic Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

036 84, 036 85, 036 86 rondorex w21

Abstract: kc 59 246 3256E
Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

kc 59 246

Abstract: 3256E
Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

3256E

Contextual Info: ispLSI 3256E High Density Programmable Logic Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

3256E

Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

3256E

Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

AC30

Abstract: AD29 AG29 AG30 AK19 AJ-31 AJ22
Contextual Info: ispLSI 3448 Functional Block Diagram J3 J2 J1 . J0 Output Routing Pool ORP H3 Output Routing Pool (ORP) H1 H0 G3 D Q D Q K1 G2 OR Array D Q K2 G1 K3 D Q D Q OR Array Twin GLB G0 D Q . • ispLSI FEATURES: — 5V In-System Programmable (ISP ) Using Lattice