OR GATES Search Results

cd4075

Abstract: CD4071 CD4072 CD4071B CD4072B CD4075B MS-001 "OR Gates"
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

CD4075

Abstract: cd4071
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

CD4071B

Abstract: CD4072B CD4075B MS-001 SCHS056D
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

motorola 223

Abstract: DL122 MC10H117
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate MC10H117 The MC10H117 dual 2–wide 2–3–input OR–AND/OR–AND–Invert gate is a general purpose logic element designed for use in data control, such as digital multiplexing or data distribution. Pin 9 is common to both gates. This MECL 10H

Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4071BP/BF/BFNJC4072BP/BF TC4075BP/BF TC4071B QUAD 2 INPUT OR GATE TC4072B DUAL 4 INPUT OR GATE TC4075B TRIPLE 3 INPUT OR GATE TC4071B, TC4075BP / BF and TC4072BP / BF are positive logic OR gates w ith tw o inputs, three inputs and fo ur inputs

DM74LS136

Abstract: DM74LS136M DM74LS136N M14A N14A block diagram of AND gate
Contextual Info: DM74LS136 Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs General Description This device contains four independent gates, each of which performs the logic exclusive-OR function. Connection Diagram Dual-In-Line Package DS009819-1 Order Number DM74LS136M or DM74LS136N

Contextual Info: SN54AC32, SN74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS528B - AUGUST 199S - REVISED SEPTEMBER 1996 SN54AC32 . . . J OR W PACKAGE SN74AC32 . . . D, DB, N, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) 1-|im Process Package Options Include Plastic

5962R8973601VDA

Contextual Info: 54ACTQ32QML 54ACTQ32QML Quiet Series Quad 2-Input OR Gate Literature Number: SNOSAM1 54ACTQ32QML Quiet Series Quad 2-Input OR Gate General Description Features The ’ACTQ32 contains four, 2-input OR gates and utilizes NSC Quiet Series technology to guarantee quiet output

Contextual Info: TYPES SN54H21, SN54LS21, SN74H21, SN74LS21 DUAL 4-INPUT P0SIT1VE-AND GATES _ REVISED APRIL 1985 SN54H21 . . . JPACKAGE SN54LS21 . . . J OR W PACKAGE S N 74H 21 . . . J OR N PACKAGE SN74LS21 . . . D, J OR N PACKAGE • * Package Options include Both Plastic and

Contextual Info: TYPES SN54S64, SN54S65, SN74S64, SN74S65 4 -2 -3 -2 INPUT AND-OR-INVERT GATES REVISED DECEMBER 1983 SN54S64, SN54S65 . . J OR W PACKAGE SN74S64, SN74S65 . . D, J OR H PACKAGE Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic

SN54AHC86

Abstract: SN74AHC86
Contextual Info: SN54AHC86, SN74AHC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS249A - OCTOBER 1995 - REVISED MARCH 1996 Operating Range 2-V to 5.5-V V qq SN54AHC86 . . . J OR W PACKAGE SN74AHC86 . . . D, DB, N, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted

Contextual Info: SN54AHCT32, SN74AHCT32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS248G – OCTOBER 1995 – REVISED OCTOBER 1998 D D D D SN54AHCT32 . . . J OR W PACKAGE SN74AHCT32 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: HARRIS CMOS Quad Exclusive-OR and Exclusive-OR Gates High-Voltage Types 20-Volt Rating CD4070B — Quad Exclusive-OR Gate CD4077B — Quad Exclusive-NOR Gate • CD4070B contains fo u r independ­ ent Exclusive-OR gates. The RCA-CD4077B contains gates.

Contextual Info: SN54AHCT86, SN74AHCT86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS250H – OCTOBER 1995 – REVISED OCTOBER 1998 D D D SN54AHCT86 . . . J OR W PACKAGE SN74AHCT86 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

HC32

Abstract: SN54HC7032 SN74HC7032
Contextual Info: SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS SC LS036A - M ARCH 1984 - R E V IS E D JANUARY 1996 • Operation From Very Slow Input Transitions • Temperature-Compensated Threshold Levels SN54HC7032 . . . J OR W PACKAGE SN74HC7032 . . . D OR N PACKAGE

KK4030B

Abstract: KK4030BD KK4030BN
Contextual Info: TECHNICAL DATA KK4030B Quad Exclusive-OR Gate High-Voltage Silicon-Gate CMOS The KK4030B types consist of four independent Exclusive-OR gates. The KK4030B provides the system designer with a means for direct implementation of the Exlusive-OR function. • Operating Voltage Range: 3.0 to 18 V

Contextual Info: SN54AHC32, SN74AHC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS247C – OCTOBER 1995 – REVISED JULY 1998 D D D SN54AHC32 . . . J OR W PACKAGE SN74AHC32 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V VCC EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 FEATURES • • • • SN54LVC86A . . . J OR W PACKAGE SN74LVC86A . . . D, DB, NS, OR PW PACKAGE TOP VIEW 3 12 4 11 5 10 6 9 7 8 VCC

Contextual Info: SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 FEATURES • • • • SN54LVC86A . . . J OR W PACKAGE SN74LVC86A . . . D, DB, NS, OR PW PACKAGE TOP VIEW 3 12 4 11 5 10 6 9 7 8 VCC

Contextual Info: GD54/74S32 QUADRUPLE 2-INPUT POSITIVE OR GATES Description The use of schottky TTL technology has enabl­ ed the achievement of high input/output voltages and high speed. This device contains four independent 2 -input OR gates. It performs the Boolean functions Y = Â B or

Contextual Info: SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 FEATURES • • • • SN54LVC86A . . . J OR W PACKAGE SN74LVC86A . . . D, DB, NS, OR PW PACKAGE TOP VIEW 3 12 4 11 5 10 6 9 7 8 VCC

Contextual Info: SN54LVC86A, SN74LVC86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES www.ti.com SCAS288P – JANUARY 1993 – REVISED APRIL 2005 FEATURES • • • • SN54LVC86A . . . J OR W PACKAGE SN74LVC86A . . . D, DB, NS, OR PW PACKAGE TOP VIEW 3 12 4 11 5 10 6 9 7 8 VCC

LV86A

Contextual Info: SN54LV86A, SN74LV86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS392C – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV86A . . . J OR W PACKAGE SN74LV86A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)