OR GATES Search Results

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

Contextual Info: SN54AHC86, SN74AHC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS249I – OCTOBER 1995 – REVISED JULY 2003 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHC86 . . . J OR W PACKAGE SN74AHC86 . . . D, DB, DGV, N, NS, OR PW PACKAGE

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y

Contextual Info: SN54HC7002, SN74HC7002 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS _ SCLS033B - MARCH 1984 - REVISED JULY 1996 • Operation From Very Slow Input Transitions SN54HC7002 . . . J OR W PACKAGE SN74HC7002. . . D OR N PACKAGE TOP VIEW

Contextual Info: 54AC11032,74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES D2957, JULY 1987 - REVISED APRIL 1993 54AC11032. . . J PACKAGE 74AC11032 . . . D, DB OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-PIn Vqc and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS076B – DECEMBER 1982 – REVISED MAY 1997 D SN54HC02 . . . J OR W PACKAGE SN74HC02 . . . D, DB, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

Contextual Info: SN54HC20, SN74HC20 DUAL 4-INPUT POSITIVE-NAND GATES SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000 D SN54HC20 . . . J OR W PACKAGE SN74HC20 . . . D, DB, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

Contextual Info: SN54F125, SN74F125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS D3211, JANUARY 1989 SN 54F125 . . . J PACKAGE SN 74F125 . . . D OR N PACKAGE 3-State Outputs Drive Bus Unes or Buffer Memory Address Registers TOP VIEW Package Options Include Standard Plastic

74ACT11086

Contextual Info: 54ACT11086, 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES T 10185— D3390, N O VEM BER 1969 54ACT11086 . . . J PACKAGE 74ACT11086 . . . D OR N PACKAGE • Inputs are TTL-Voltage Compatible • Flow-Through Architecture to Optimize PCB Layout TOP VIEW

Contextual Info: SN54AHCT32, SN74AHCT32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS248L – OCTOBER 1995 – REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT32 . . . J OR W PACKAGE SN74AHCT32 . . . D, DB, DGV, N, NS,

Contextual Info: SN54AHCT32, SN74AHCT32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS248L – OCTOBER 1995 – REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT32 . . . J OR W PACKAGE SN74AHCT32 . . . D, DB, DGV, N, NS,

TEXAS HB126

Abstract: HB126 AHCT126 A115-A SN54AHCT126 SN74AHCT126 SN74AHCT126D SN74AHCT126N hb126 TEXAS INSTRUMENTS
Contextual Info: SN54AHCT126, SN74AHCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS265N – DECEMBER 1995 – REVISED APRIL 2002 D D D SN54AHCT126 . . . J OR W PACKAGE SN74AHCT126 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible

Contextual Info: SN54AHCT86, SN74AHCT86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS250M – OCTOBER 1995 – REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT86 . . . J OR W PACKAGE SN74AHCT86 . . . D, DB, DGV, N, NS,

74LVQ32

Abstract: 74LVQ32SC 74LVQ32SCX 74LVQ32SJ 74LVQ32SJX M14A
Contextual Info: LVQ32 National Semiconductor 74LVQ32 Low Voltage Quad 2-Input OR Gate General Description Features The LVQ32 contains four, 2-input OR gates. • ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dy­ namic threshold performance

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS523B – AUGUST 1995 – REVISED AUGUST 1999 D D D SN54ACT00 . . . J OR W PACKAGE SN74ACT00 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS523B – AUGUST 1995 – REVISED AUGUST 1999 D D D SN54ACT00 . . . J OR W PACKAGE SN74ACT00 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS366G – MAY 1997 – REVISED APRIL 2002 D D D D D SN54AHCT132 . . . J OR W PACKAGE SN74AHCT132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible

Contextual Info: SN54F86, SN74F86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SDFS019B – JANUARY 1989 – REVISED JANUARY 1997 D SN54F86 . . . J PACKAGE SN74F86 . . . D OR N PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and

Contextual Info: SN54F32, SN74F32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SDFS044B – MARCH 1987 – REVISED MAY 1999 D SN54F32 . . . J PACKAGE SN74F32 . . . D OR N PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and

eNAND

Contextual Info: SN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS366G – MAY 1997 – REVISED APRIL 2002 D D D D D SN54AHCT132 . . . J OR W PACKAGE SN74AHCT132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible

Contextual Info: SN54LS21, SN74LS21 DUAL 4-INPUT POSITIVE-AND GATES APRIL 1 9 8 5 - SN54LS21 . . . J OR W PACKAGE SN74LS21 . . . D OR N PACKAGE Package Options Include Plastic "Sm all O u tline " Packages. Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs

Contextual Info: TC4085BP C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4085BP DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE TC4085BP contains two circuits of AND-OR select gates and the outputs are inverted. The circuit consists of two 2 input AND gates and one NOR gate,

Contextual Info: SN54AHCT00, SN74AHCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS229F – OCTOBER 1995 – REVISED OCTOBER 1998 D D D SN54AHCT00 . . . J OR W PACKAGE SN74AHCT00 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54AHCT125, SN74AHCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS284A - DECEM BER 1995 - REVISED MARCH 1996 • • • SN54A HC T125. . . J OR W PACKAGE SN74AHCT125 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted