OR GATES Search Results

cd4075

Abstract: CD4071 CD4072 CD4071B CD4072B CD4075B MS-001 "OR Gates"
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

Contextual Info: SN54AHCT32, SN74AHCT32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS248G – OCTOBER 1995 – REVISED OCTOBER 1998 D D D D SN54AHCT32 . . . J OR W PACKAGE SN74AHCT32 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54AHC32, SN74AHC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS247C – OCTOBER 1995 – REVISED JULY 1998 D D D SN54AHC32 . . . J OR W PACKAGE SN74AHC32 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V VCC EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54AHC86, SN74AHC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS249I – OCTOBER 1995 – REVISED JULY 2003 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHC86 . . . J OR W PACKAGE SN74AHC86 . . . D, DB, DGV, N, NS, OR PW PACKAGE

Contextual Info: S32 National ÆÎà Semiconductor DM54S32/DM74S32 Quad 2-Input OR Gates General Description This device contains four independent gates each of which performs the logic OR function. Connection Diagram Dual-ln-Une Package Vcc B4 A4 Y4 B3 A3 Y3 Tl/F/6452-1 Order Number DMS4S32J, DM54S32W or DM74S32N

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y

74LS32 function table

Contextual Info: GD54/74LS32 QUADRUPLE 2-INPUT POSITIVE OR GATES Description Pin Configuration This device contains four independent 2-input OR gates. It performs the Boolean functions V = Â • B or Y = A + B in positive logic. Vcc 14 4B 13 4A 12 4Y 11 38 10 3A 3Y 9 8 [¿-I

SL4071B

Abstract: SL4071BD SL4071BN
Contextual Info: SL4071B Quad 2-Input OR Gate High-Voltage Silicon-Gate CMOS The SL4071B OR gates provide the system designer wich direct emplementation of the positive-logic OR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C

Contextual Info: SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SDAS006B – APRIL 1982 – REVISED DECEMBER 1994 • SN54ALS86, SN54AS86A . . . J PACKAGE SN74ALS86, SN74AS86A . . . D OR N PACKAGE TOP VIEW Package Options Include Plastic

Contextual Info: SN54HC7002, SN74HC7002 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS _ SCLS033B - MARCH 1984 - REVISED JULY 1996 • Operation From Very Slow Input Transitions SN54HC7002 . . . J OR W PACKAGE SN74HC7002. . . D OR N PACKAGE TOP VIEW

GAL programmer schematic

Abstract: schematic set top box abv 1000 inverter GAL programming Guide vhdl projects abstract and coding ABEL-HDL Reference Manual gal programmer gal programming algorithm ieee floating point vhdl new ieee programs in vhdl and verilog
Contextual Info: ispDesignExpert User Manual Version 8.0 Technical Support Line: 1-800-LATTICE or 408 428-6414 DE-UM Rev 8.0.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

54LS32

Abstract: a 6361 54LS32/DM54LS32/DM74LS32 54LS32DMQB 54LS32FMQB 54LS32LMQB DM54LS32 DM54LS32J DM54LS32W DM74LS32
Contextual Info: 54LS32 DM54LS32 DM74LS32 Quad 2-Input OR Gates General Description Features This device contains four independent gates each of which performs the logic OR function Y Alternate Military Aerospace device 54LS32 is available Contact a National Semiconductor Sales Office

Contextual Info: c* SY10EL01 SY100EL01 4-INPUT OR/NOR SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • 230ps propagation delay The SY10/100EL01 are 4-input OR/OR gates. These devices are functionally equivalent to the E101 devices, with higher performance capabilities. With propagation

IL44

Abstract: ASYNCHRONOUS COUNTER UP FUNCTION OF PRESET 1-BIT D Latch IL44 J FD14E 2 SD 106 AI OL41s 8 shift register by using D flip-flop ID31E OD34E
Contextual Info: ispLSI 5K/8K Macro Library Supplement Version 8.0 Technical Support Line: 1- 800-LATTICE or 408 428-6414 DSNEXP-ISPMLS Rev 8.01 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

conversion software jedec lattice

Abstract: electronic componets list datasheet radix delta ap verilog code to generate square wave ABEL-HDL Reference Manual cut template DRAWING dot matrix printer circuit diagram datasheet LSC 132 new ieee programs in vhdl and verilog V0008
Contextual Info: Design Verification Tools User Manual Version 8.0 Technical Support Line: 1- 800-LATTICE or 408 428-6414 DE-VM Rev 8.0.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

6z130

Abstract: switched reluctance motor IGBT 0-15V AN461 TD300 SCHEMATIC POWER SUPPLY WITH IGBTS 6 switched reluctance motor IGBT application note motors used in IGBT Amplifier
Contextual Info: TECHNICAL NOTE  TD300 USED IN POWER MOS AND IGBT DRIVING by R. LIOU INTRODUCTION TD300 is designed to drive up to three Power MOS or IGBTs low side and/or high side from CMOS or LSTTL logic signals, or pulse transformers. It integrates: three buffers,

blackjack vhdl code

Abstract: ABEL-HDL Reference Manual asynchronous 4bit up down counter using jk flip flop GAL1 vhdl code for BCD to binary adder 7449 decoder and seven segment display diode 7449 STH 8450 traffic light controller vhdl coding transistor manual substitution FREE DOWNLOAD
Contextual Info: ABEL-HDL Reference Manual Version 8.0 Technical Support Line: 1- 800-LATTICE or 408 428-6414 DSNEXP-ABL-RM Rev 8.0.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

Contextual Info: TC4030BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4030BP,TC4030BF,TC4030BFN TC4030B Quad Exclusive-OR Gate TC4030B contains four circuits of exclusive OR gates. Since the buffers of two stage inverters are provided for all the outputs, the

Contextual Info: 54AC11032,74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES D2957, JULY 1987 - REVISED APRIL 1993 54AC11032. . . J PACKAGE 74AC11032 . . . D, DB OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-PIn Vqc and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: SN54AHCT125, SN74AHCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS264J – DECEMBER 1995 – REVISED OCTOBER 1998 D D D SN54AHCT125 . . . J OR W PACKAGE SN74AHCT125 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible

Contextual Info: SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS076B – DECEMBER 1982 – REVISED MAY 1997 D SN54HC02 . . . J OR W PACKAGE SN74HC02 . . . D, DB, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

74AC86

Abstract: 74AC86MTC 74AC86PC 74AC86SC 74AC86SJ AC86 M14A M14D MTC14 N14A
Contextual Info: Revised October 1998 74AC86 Quad 2-Input Exclusive-OR Gate General Description Features The AC86 contains four, 2-input exclusive-OR gates. • ICC reduced by 50% ■ Outputs source/sink 24 mA Ordering Code: Order Number 74AC86SC 74AC86SJ 74AC86MTC 74AC86PC

Contextual Info: SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS076B – DECEMBER 1982 – REVISED MAY 1997 D SN54HC02 . . . J OR W PACKAGE SN74HC02 . . . D, DB, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Shrink Small-Outline