OLD AGE DATA Search Results

nortel meridian

Contextual Info: Hello Direct Uses Clarify eFrontOffice to Fulfill its Customer-Focused Web Vision Hello Direct became an $80 million direct marketing leader by adhering to an age-old adage: find a need and fill it. That need is providing small businesses with personalized

ATT 41

Contextual Info: — — Microelectronics 41MF2 Quad Differential Line Receiver Features Description • 1000 V CDM and 1000 V HBM input ESD rating The 41M F2 Q uad Differential Line R eceiver inte­ grated circuits receive digital data over balanced transm ission lines. T hese receivers translate differ­

ATT 41

Contextual Info: Microelectronics 41LF2 Quad Differential Line Receiver Features Description • 2000 V CDM and 2000 V HBM input ESD rating The 41LF2 Q uad D ifferential Line R eceiver inte­ grated circuits receive digital data over balanced transm ission lines. T hese receivers translate differ­

8085 microprocessor opcode

Abstract: opcode table for 8086 microprocessor 8085 microprocessor new applications 6502 microprocessor 8085 microprocessor remote controls applications 8086 opcode table for 8086 microprocessor MD68SC49BD Z8000 MD68SC49BC MD68SC49BE
Contextual Info: ISO-CMOS M068SC49B Bus Monitor Preli m in aryl nf ojm ation Features , Pin Connections « Address ra n g e checking. • Data p attern match/m ism atch detection. •C o n tro l bus condition checking. »S in g le or m ulti-pass mode. •F re e z e or continuous output.

Contextual Info: IBM11M32735B IBM11M32735C 32M x 72 DRAM Module Features • 168 Pin JEDEC Standard, 8 Byte Dual In-line Memory Module • System Performance Benefits: - Buffered inputs except RAS, Data - Reduced noise (32 VSs/V cc P^s) - 4 Byte Interleave enabled - Buffered PDs

Contextual Info: IBM11T1645LP 1M x 64 144 PIN SO DIMM Features Au contacts Optimized for byte-write non-parity applications • 144 Pin JEDEC Standard, 8 Byte Small Outline Dual In-line Memory Module with 8 Byte busses • 1 Mx64 Extended Data Out SO DIMM • Performance:

Contextual Info: I =¥= = = = ’= IBM11N16845BB IBM11N16845CB Preliminary 16M x 72 Super EOS Module Features • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-line Memory Module • 16Mx72 Extended Data Out Page Mode DIMMs • Performance: tcAc ! tftA t:;c i tnpc Provides Chip-Kill ECC protection transparently to

ER2051HR

Abstract: earom VSS-15 C5VI ER2051 MNOS memory ER2051IR 263C2
Contextual Info: ER2051 ER2Ü51IR ER2051HR 512 Bit Electrically Alterable Read Only Memory • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 32 Word x 16 B it O rganization 5 Bit B ina ry Addressing + 5 , - 2 8 V Power Supplies Word Alterable 10 Year Data Storage fo r ER2051 at - 7 0 ° C

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT 32M-BIT M ASK-PRO G RAM M ABLE ROM 4M-WORD BY 8-BIT BYTE MODE /2M-WORD BY 16-BIT (WORD MODE) PAGE ACCESS MODE Description The ¿¡PD23C32040L is a 33,554,432 bits m ask-program m able ROM. The w ord organization is selectable (BYTE

Contextual Info: H D63085-Document Image Compression and Expansion Processor D I C E P The DICEP is an LSI that performs com pres­ sion (encoding) and expansion (decoding) of th e digital (tw o-value) data rep resen tin g a docum ent im age. The DICEP is u sed in G3 and G4 facsim ile

Stag solar Programmers

Contextual Info: PROM PROGRAMMERS STAG PROGRAMMERS Solar • ■ ■ ■ ■ ■ ■ Completely stand-alone operation Simple PC connection via Stag Com DOS/Windows* software Gang and set programming capability 16-Mbit RAM as standard Expandable to 64 Mbits of RAM Powerful data editing tools

Contextual Info: GoldStar GOLDSTAR ELECTRON CO., LTD. Description GMM7364000BS/BSG-60/70/80 4,194,304 WORDS x 36 BIT CMOS DYNAMIC RAM MODULE Features The GMM7364000BS/BSG is a 4M x36 Bits dy­ • 72 pins Single In-Line Package GMM736XXXXBS: Tin-Lead Plate namic RAM MODULE which is assembled 36

MCS-85

Abstract: MCS-48 MCS48 9114 RAM I8741A MCS-80 intel iapx mcs 48
Contextual Info: illt o l P E & D M D IM IiW ” I 8 7 4 1 A UNIVERSAL PERIPHERAL INTERFACE 8-BIT MICROCOMPUTER INDUSTRIAL • 8-Bit CPU plus EPROM, RAM, I/O, Timer and Clock in a Single Package . One 8-Bit Status and Two Data Registers for Asynchronous Slave-to-Master Interface

T74LS75B1

Abstract: T54LS75D2
Contextual Info: I PRELIMINARY DATA 4-BIT D LATCH DESCRIPTION The T54LS/T74LS75 is a 4-bit D latch; it is applied as temporary storage for binary information bet­ ween processing units and input/output or indica­ tor units. When the Enable is HIGH, the information present at a data D input shifts to the Q output,

cardiac pacemaker

Contextual Info: Instruction Manual Full Body Sensor Body Composition Monitor and Scale Model HBF-516 Before Using the Monitor TABLE OF CONTENTS Before Using the Monitor Introduction . 3

Contextual Info: Rev 0. GoldStar GOLDSTAR ELECTRON CO, LTD. G M M 7 3 2 4 0 0 0 B S /B S G - 6 0 /7 0 /8 0 4,194,304 WORDS x 32 BIT CMOS DYNAMIC RAM MODULE Description Features The GMM7324000BS/BSG is a 4M x32 Bits dy­ namic RAM MODULE which is assembled 36 pieces of 4Mx 1 bit DRAMs in 20/26 pin SOJ pack­

Contextual Info: EL2Q19C Fast, High Voltage Comparai «ter Slave Flip-Flop HIGH PERFORMANCE ANALOG INTEGRATED CfflOHTS F e a tu r e s G en era l D e sc r ip tio n • Comparator cannot oscillate • F ast response—5 ns data to clock setup, 20 ns clock to output • Wide input differential voltage

hc 7400

Abstract: Signetics 2533 7400 hc 7400 TTL IN8050 25C-2
Contextual Info: 2533-N DESCRIPTION The 2533 s ta tic s h ift re gister con sists of enhancem ent m ode p -chann el s ilic o n gate MOS devices inte grated on a sin g le m o no­ lith ic chip. The 1024-bit re gister is eq uippe d w ith 2 data inpu ts to g e th e r w ith a stream select c o n tro l

AN1000CS

Abstract: PLC192 PLC1000A ten pao transformer PLC-1000 Adaptive Networks PLC1000D universal powerline modem PLC1000 PLC-192
Contextual Info: AN1000 X i] V J A D A P T IV E P o w e rlin e N e tw o rk C o m m u n ic a tio n s C h ip Set N E TW O R K S Features * 100 kbps Data Communications Rate, 268.8 kbps Raw Data Rate * Reliable as Dedicated Wiring, Bit Error Rate < 1CT * Supports Up To 65,534 Nodes per Network

Contextual Info: RX2020 916.5 MHz ASH Receiver • • Ideal f o r 916.5 M H z, 3 V D a ta R eceivers in Europe H igh-Sensitivity P assive D esign with N o R F O scillation Use with H X 2 0 0 0 fo r 19.2 kbps D a ta R ate Sim ple to A pply with E xternal P a rts Count •

Contextual Info: 4 ,1 9 4 ,3 0 4 W O R D X This is advanced information and specifica- T -4 4 - 2 3 - 1r tions are subject to change without notice. 1 BIT D Y N A M IC R A M DESCRIPTION The TC514100APL/AJL/ASJL/AZL is the new generation dynamic RAM organized 4,194,304 words by

8735C

Contextual Info: IBM11N8645B IBM11N8735B IBM11N8645C IBM11N8735C 8M x 64/72 DRAM MODULE Features • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-line Memory Module • System Performance Benefits: -Non buffered for increased performance • 8Mx64, 8Mx72 Dual Bank Extended Data Out

philips ferroxcube

Abstract: 2213P-A600-3B ferroxcube Ee core IC8012 2213p
Contextual Info: MIC8012 Liquid Crystal Display Driver General Description Features The MIC8012 driver is designed for use with liquid crystal displays. A serial data interface is used to load an internal register, which in turn controls the segment outputs. An onchip backplane oscillator is included.

Contextual Info: 6/7/13 TDK - Inductors Coils - Part No: MLZ2012M1R0HT000 Characteristics MLZ2012M1R0HT000 Multilayer Inductor for Power Line C ate gory : Inductors (Coils) Sub C ate gory : Inductor Coils TDK Se rie s Nam e : MLZ Series Application : No Data Available. Function : No Data Available.