O30PF Search Results

Contextual Info: 3.3V SYNC DRAM PLL Clock Driver Q QS52510A advance INFORMATION Q u a l it y S em iconductor , I n c . FEATURES/BENEFITS DESCRIPTION • • The Q S 5 2 5 10A is a high perform ance, low skew, low jitter, m ultiple output phase lock loop clock driver. It is designed to interface w ith the high-speed SD R AM

Contextual Info: QS52509A 3.3V SYNC DRAM PLL Clock Driver ADVANCE INFORMATION Q u a l it y S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • Intel PC-100/spread spectrum compliant • 10 outputs: 1 bank of 4, 1 bank of 5, and 1 dedicated output for feedback

TV SCHEMA

Abstract: AD201AH 50kD 100lK AD201A AD301A AD301AL 2kd 60
Contextual Info: r-. ANALOG W DEVICES GeneralPurposeLow Cost IC Operational Amplifier FEATURES Low Bias and Offset Current Single Capacitor External Compensation for Operating Flexibility Nullable Offset Voltage No Latch-Up Fully Short Circuit Protected Wide Operating Voltage Range

IR 1838 T

Abstract: 1838 pin configuration ir IR 1838 T Pin number IR 1838 1838 T IR 1838 TO PIN DIAGRAM 1838 t pin diagram 1838 ir IR 1838 3.3 v CS40
Contextual Info: CYM1838 PRELIMINARY CYPRESS 128K x 32 Static RAM Module Features Functional Description • High-density 4-megabit SRAM module • High-speed CMOS SRAMs — Access time of 25 ns • 66-pin, 1.1-inch-square PGA package • Low active power — 4.0W max. • Hermetic SMD technology

diode SKE 1/17

Abstract: diode SKE 1/16
Contextual Info: 3.3V SYNC DRAM PLL Clock Driver Q QS52510A advance INFORMATION Q u a l it y S em iconductor , I n c . FEATURES/BENEFITS DESCRIPTION • • The Q S 5 2 5 10A is a high perform ance, low skew, low jitter, m ultiple output phase lock loop clock driver. It is designed to interface w ith the high-speed SD R AM

Contextual Info: MITSUBISHI LSIs M5M5189BP, J- IS, -20, -25 6 5 5 36 -B IT 16384-W ORD BY 4-BIT CMOS STATIC RAM D E S C R IP T IO N This is a family of 16384 w ord by 4-bit static R A M s, fabri­ cated with the high-performance C M O S silicon-gate M O S process and designed for high-speed application. These

Contextual Info: 3.3V SYNC DRAM PLL Clock Driver QS52509A ADVANCE INFORMATION Q uality Semiconductor, I nc . FEATURES/BENEFITS DESCRIPTION • Intel PC-100/spread spectrum compliant • 10 outputs: 1 bank of 4, 1 bank of 5, and 1 dedicated output for feedback • Balanced drive outputs: ±12mA

Contextual Info: 3.3V SYNC DRAM PLL Clock Driver Q uality QS52510A ADVANCE INFORMATION Semiconductor, I nc. FEATURES/BENEFITS DESCRIPTION • Intel PC-100/spread spectrum compliant • 11 outputs: one bank of 10, and 1 dedicated output for feedback • Balanced drive outputs: ±12mA

Contextual Info: HM621100A Series Preliminary 1,048,576-Word x 1-Bit High Speed CMOS Static Ram • DESCRIPTION The HM621100A is a high speed 1M Static RAM organized as 1,048,576-word x 1-bit. It realizes high speed access time 20/25/35 ns and low power consumption, employing CMOS process technology

xsxx

Contextual Info: MOSEL MS76502A MAY 1992 256 x 16 BI-DIRECTIONAL FIFO WITH PARITY GENERATOR/CHECKER FEATURES DESCRIPTION • 256 x 16 bi-directional FIFO The MS76502A is an asynchronous 256 x 16 BiFlFO using adual port RAM based architecture. The MS76502 has two 16-bit bi-directional data ports. User can select

Contextual Info: 3.3V SYNC DRAM PLL Clock Driver QS52509A ADVANCE INFORMATION Q uality S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • • The QS52509A is a high performance, low skew, low jitter, multiple output phase lock loop clock driver. It is designed to interface with the high-speed SDRAM

Contextual Info: HM62932 Series Preliminary 32,768-Word x 9-Bit High Speed CMOS Static Ram I FEATURES High speed: fast access time 15/20 ns max Low Power Standby: 15^W (typ.) (L-version) Operation: 350mW (typ.) Single 5V supply Completely static memory No clock or timing strobe required

Contextual Info: TOSHIBA MOS MEMORY PRODUCTS TMM2018AP-25' TMM2018AP-35, TMM2018ÄP-45 iDESCRIPTIONl The TMM2018AP is a 16,384 bits high speed and low power static random access memory organized as 2,048 words by 8 bits and operates from a single 5V supply. Toshiba's high performance device technology provides both high speed and low power

Contextual Info: QS52509A 3.3V SYNC DRAM PLL Clock Driver ADVANCE INFORMATION Q u a l it y S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • Intel PC-100/spread spectrum compliant • 10 outputs: 1 bank of 4, 1 bank of 5, and 1 dedicated output for feedback

km6161002j15

Contextual Info: PRELIMINARY KM6161002 CMOS SRAM 65,536 W O R D x 16 Bit High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time: 15, 17, 20ns Max. • Low Power Dissipation Standby (TTL) : 40mA (Max.) (CMOS) : 10mA (Max.) Operating KM6161002J-15: 230mA (Max.)

Contextual Info: IMAGE UNAVAILABLE • Q743D1D SÖ3 ■ GL 3301 SYMBOL MIN. TYP. MAX. UNIT E17E16 Voltage at Pin 1 7 -V oltage at Pin 16 -0 .3 0.3 V D.C Voltage Difference Between any demod. output E16E15 Voltage at Pin 16 -Voltage at Pin 1 5 -0 .3 0.3 V D.C Voltage Difference

Contextual Info: 3.3V SYNC DRAM PLL Clock Driver QS52510A ADVANCE INFORMATION Q u a l it y S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • Intel PC-100/spread spectrum compliant • 11 outputs: one bank of 10, and 1 dedicated output for feedback • Balanced drive outputs: ±12mA

PC-100

Abstract: TSK1V
Contextual Info: ö 3.3V SYNC DRAM PLL Clock Driver QS52510A advance INFORMATION Q u a l it y S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • • The QS52510A is a high performance, low skew, low jitter, multiple output phase lock loop clock driver. It

Contextual Info: SONY CXK77V181 OGB/TM -9 /1 0 /1 2 65,536-Word-by-18-Bit High-Speed CMOS Synchronous Static RAM Preliminary Description Features The CXK77V1810GB/TM is a high-speed CMOS syn­ chronous static RAM with common I/O pins, organized as 65,536-words-by-18-bits. This synchronous SRAM

7641pc

Abstract: 7641 prom
Contextual Info: M MCM7641 MCM7641A M O T O R O L A T h e M C M 7 6 4 1 a n d M C M 7 6 4 1 A , t o g e t h e r w it h v a r io u s o t h e r 7 6 x x s e r ie s T T L P R O M S , c o m p r is e a c o m p le t e a n d c o m p a t ib le f a m ily h a v in g c o m m o n d c e l e c t r i c a l c h a r a c t e r i s t i c s a n d i d e n t i c a l p r o ­

500D

Abstract: CDC2509B PC-100 OPF 345 diode
Contextual Info: 3.3V SYNC DRAM PLL Clock Driver Q u a l it y QS52509A ADVANCE INFORMATION S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • • The QS52509A is a high performance, low skew, low jitter, multiple output phase lock loop clock driver. It is