O REGISTERS Search Results

Contextual Info: FAST C M O S 16-BIT BUS TRANSCEIVER/ REGISTERS FEATURES: • C o m m o n features: 0.5 M IC R O N C M O S T e c h n o lo g y - H i g h- spe ed , l o w - p o w e r C M O S r e p l a c e m e n t for A BT f unct i ons - Typi cal tSK o ( O ut pu t S k e w) < 250ps

MC6802

Abstract: MC6808 MC6802P SSC 9500 MC68B02P MC6802CL P8BU MC6800 pin diagram block diagram of mri machine M6800
Contextual Info: MC6802 MC6808 MC6802NS M O T O R O L A M IC R O P R O C E S S O R W IT H C LOCK A N D O P T IO N A L R A M The M C6802 is a m o n o lith ic 8 -b it m icroprocessor th a t c o n ta in s all the registers and a ccum ulato rs o f th e present M C6800 plus an internal clock

Contextual Info: PERFORMANCE SEMICONDUCTOR 50E D T O b S S 11 ? O O O O fllS 4 P54/74PCT651/651A P54/74PCT652/652A OCTAL TRANSCEIVERS/REGISTER ^ - FEATURES • Full CMOS Implementation Bidirectional Bus Transceiver and Registers ■ Low Power Operation

SA14-2093-00

Abstract: powerpc 476 SPR529 ibm powerpc 470
Contextual Info: SA14-2093-00&#39; ' \S'ò‘r5i ‘C/nboi ïV o n to e f MPCPRGREF/D ^ \l\o \o ro \a O rd e r N um b er) PowerPC Microprocessor Family: The Programmer’s Pocket Reference Guide P o w erP C m o to r o la Introduction This document provides an overview of the PowerPC™ registers, instructions, and

Contextual Info: MC14014B MC14021B M O TO R O LA C M O S M SI < L O W -P O W E R C O M P L E M E N T A R Y M O S 8 BIT STATIC SH IFT REGISTER The M C 1 4 0 1 4 8 and M C 1 4 0 2 1 B 8 -b it s ta tic s h ift registers are c o n s tru c te d w ith M O S P-channel and N channel enhancem ent m ode

3tf47

Abstract: DN164 ef6821 cm 68006 4N06 PL2041
Contextual Info: rZ ^ 7 T # S G S -T H O M S O N s [L iO T M O i TS68008 8/16—BIT M IC R O P R O C E S S O R W ITH 8 -B IT DATA BUS • ■ ■ ■ ■ ■ ■ 17 32-BIT DATA AND ADDRESS REGISTERS 56 BASIC INSTRUCTION TYPES EXTENSIVE EXCEPTION PROCESSING MEMORY MAPPED I/O

Contextual Info: CL-PD6729 PCI-to-PCMCIA Host Adapter 'CIRRUS LOGIC 8. I/O WINDOW MAPPING REGISTERS CAUTION: Be sure that the I/O windows do not map to the Base Address 0 register programmed at offset 10h. 8.1 I/O W in d o w C o n tro l Register Name: I/O Window Control Index: 07h

Contextual Info: TMX320C6201 DIGITAL SIGNAL PROCESSOR SPRS051B - JANUARY 1997 - REVISED JUNE 1997 Highest Performance Fixed-Point Digital Signal Processor DSP : GGP 352-PIN BGA PACKAGE (BO TTO M V IE W ) I 26 o o o o o o o o o o o o o o o o o o o o o o o o o o - 1 600 MIPS @ 200 MHz

QFP-44

Abstract: tcon 480Hz P24SS
Contextual Info: VMX51C1016 Datasheet Rev 1.1 Versa Mix 8051 Mixed-Signal MCU Overview Feature Set o o o o o o o o o o o o o o o o o o o o Applications Automotive Applications Industrial Controls / Instrumentation Consumer Products Medical Devices FIGURE 1: VMX51C1016 BLOCK DIAGRAM

QFP-44

Abstract: VMX1C1016
Contextual Info: VMX1C1016 Datasheet Rev 1.0 Versa Mix 8051 Mixed-Signal MCU Overview Feature Set o o o o o o o o o o o o o o o o o o o o Applications Automotive Applications Industrial Controls / Instrumentation Consumer Products Medical Devices FIGURE 1: VMX51C1016 BLOCK DIAGRAM

THx 208

Abstract: string quartet QFP-44 VMX1C1016 i2c interfacing with 8051 asm code barrel shifter VMX1C1 j1708 to RS232 converter
Contextual Info: VMX1C1016 Datasheet Rev 1.0 Versa Mix 8051 Mixed-Signal MCU Overview Feature Set o o o o o o o o o o o o o o o o o o o o Applications Automotive Applications Industrial Controls / Instrumentation Consumer Products Medical Devices FIGURE 1: VMX51C1016 BLOCK DIAGRAM

alu 7481

Abstract: 7486 Logic ICs MC88000 7481 memory ics DSP96002 shift register 7491 74181 introduced 96002 manual MCM511002
Contextual Info: SECTION 7 EXPANSION PORTS AND I/O PERIPHERALS 7.1 INTRODUCTION The upper 128 locations of the X and Y Data memories are defined as the I/O space. The Y memory I/O space is wholly external, while the X memory I/O space is internal. The X memory I/O space is used to address the I/O Interface registers as well as the bus, port select and interrupt control registers. Both I/O spaces may be accessed by regular X and Y memory MOVE instructions. The MOVEP instructions offer I/O

4021B

Abstract: s4014 HCF4021b HCF4014B
Contextual Info: r z 7 S C S -T H O M S O N Ä 7# HCC/HCF4014B HCC/HCF4021B MDœmiOïïGMDûi 8-STAGE STATIC SHIFT REGISTERS 4014B S Y N C H R O N O U S P A R A L L E L OR S E R IA L IN P U T /S E R IA L O U T P U T 4021B A SYNCHRO NO US PARALLEL IN P U T O R S Y N C H R O N O U S

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM62982 Advance Information 64K x 4 Bit Fast Synchronous Static RAM with Output Registers T h e M C M 6 2 9 8 2 is a 2 6 2 . 1 4 4 b it s y n c h r o n o u s s t a t ic r a n d o m a c c e s s m e m o r y o r g a n iz e d a s 6 5 , 5 3 6 w o r d s o f 4 b its , f a b r ic a t e d u s in g M o t o r o la ’s h ig h - p e r f o r m a n c e

ST19XT34

Abstract: D290 ISO7816 ISO7816-3
Contextual Info: ST19XT34 Smartcard MCU with MAP, USB/ISO Interface & 34 Kbytes High Density EEPROM DATA BRIEF t e l o bs O • ■ ■ ■ o r P Figure 1. Delivery Form e t le o s b O - c u d s t Notch 4 r P e ■ 4 u d o ■ FIPS 140-2 COMPLIANT RANDOM NUMBER GENERATOR WITH TWO GUN REGISTERS

2952A

Contextual Info: Eight-Bit Bidirectional I/O Ports with Handshake DISTINCTIVE CHARACTERISTICS E ig h t-B it, B id ire c tio n a l I/O P o rt - Inverting and Non-Inverting Versions - Tw o eight-bit, back-to-back registers store data moving in both directions between tw o bidirectional busses.

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM6293 16K x 4 Bit Synchronous Static RAM with Output Registers T h e M C M 6 2 9 3 is a 6 5 , 5 3 6 b it s y n c h r o n o u s s t a t ic r a n d o m a c c e s s m e m o r y o r g a n iz e d a s 1 6 , 3 8 4 w o r d s o f 4 b its , f a b r ic a t e d u s in g M o t o r o la 's s e c o n d - g e n e r a t io n h ig h - p e r ­

EI96

Contextual Info: 8 0 9 60 JD 1.0 PURPOSE attrib u te s th ro u g h m e m o r y - m a p p e d co ntro l registers M M R s — an e x t e n s i o n n o t f o u n d on t h e ¡960 Kx, T h i s d o c u m e n t c o n t a i n s a d v a n c e i n f o r m a t i o n fo r the 80960JD

Contextual Info: Q CM O S 4 x 4 Multiport Register High-Voltage T y p e s 20-V o lt Rating The flC A -C 0 4 0 20 8 B is a 4 x 4 m u ltip o rt register containing fo u r 4-bit registers, w rite address decoder, tw o separate read address decoders, and tw o 3-state o u tp u t buses.

dps 298 cp 2

Abstract: 286 dram schematic 85A9 k2 dsc hen ng dps 298 cp UltraSPARC ii FRS 8C - 05 9V DC
Contextual Info: if 4 4 o Q O o < o o f O O O I O o o o < I O O O O ( 5 o ò o ° 5 ‘ o o < o Dual Processor System Controller (DSC) Prelim in ary Data Sheet O c to b e r 1 996 S T P 220 2B G A S un M icroelectronics October 1996 U lt r a S P A R C DATA SHEET - I/II

Contextual Info: O K I Semiconductor MSM6778 120-DQT C O M M O N DRIVER TCP GENERAL DESCRIPTION The M SM 6778 is a L C D dot-m atrix com m on driver. Fabricated in C M O S technology, the device contains tw o 60-bit b idirectional shift registers, level shifters, and 4-level drivers.

KS0789

Abstract: ic 245
Contextual Info: PRELIMINARY CMOS DIGITAL INTEGRATED CIRCUIT KS0789 Introduction 100 channel C o m m o n d rive r fo r LCD DOT MATRIX, KS 0789 is a LCD d rive r LSI w hich is fa b ric a te d by low p o w e r C M O S high vo lta g e p roce ss te ch n olo gy. T his device c o n s is ts o f tw o 50 b it B idire ctlo n s h ift registers

D2999

Contextual Info: SN65558, SN75558 ELECTROLUMINESCENT ROW DRIVERS SLDSD18B - D2999, DECEMBER 195 - REVISED APRIL 1993 • Each Device Drives 32 Electrodes FN PACKAGE {TOP VIEW N O t l O » K O O # O r <t V— T - 1 - 1 - 1 - Y - 1 - 1 - W O J O O O O O O O O O O O Z • High-Voltage Open-Collector NPN Outputs

74ls series

Abstract: 74ls series logic 74LS SPXXHC80 SPXXHC82
Contextual Info: SPXXHC80 SPXXHC82 SPXXHC298 54/74 Series Adders/Registers Ordering Information • U tiliz e s S P I’s S e le c tiv e O x id a t io n , S ilic o n - G a t e C M O S P ro c e s s . ■ S p e e d , f u n c t io n a n d p in - o u t c o m p a t ib le t o 7 4 L S s e rie s L o g ic .