NS 332 Search Results

Contextual Info: M O S E L V IT E U C V52C4256 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512 X 4 SAM 60 70 80 10 Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns 100 ns Max. CAS Access Time, (tcAC) 15 ns 20 ns 25 ns 25 ns Max. Column Address Access Time, (t*) 30 ns 35 ns 40 ns

Contextual Info: MOSEL- VITELIC V52C4256 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 5 1 2 X 4 SAM HIGH PERFORMANCE V52C4256 60 PRELIMINARY 80 10 70 ns 80 ns 100 ns 20 ns 25 ns 25 ns 40 ns 50 ns 70 Max. RAS Access Time, tp^c 60 ns Max. CAS Access Time, <tQAC) 15 ns Max. Column Address Access Time, (tAA)

Contextual Info: M O SEL VETEUC V52C4256 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512 X 4 SAM HIGH PERFORMANCE V52C4256 60 70 80 10 Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns 100 ns Max. CAS Access Time, (tCAC) 15 ns 20 ns 25 ns 25 ns Max. Column Address Access Time, (1M )

yrm 620

Contextual Info: ijf r VITEUC V53C104B HIGH PERFORMANCE, LO W POWER 256K X 4 B IT FAST PAGE MODE CMOS DYNAMIC RAM 60/60L 70/70L 80/80L Max RAS Access Time, t„ . _ 1 RAC' 60 ns 70 ns 80 ns Max Column Address Access Time, (*CAA) 30 ns 35 ns 4 0 ns Min Fast Page Mode Cyde Time, (tpç)

Contextual Info: DALLAS SEMICONDUCTOR DS1020 Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay C7 IN [ • Models with 0.15 ns, 0.25 ns, 0.5 ns, 1 ns, and 2 ns steps • Leading and trailing edge accuracy 16 ] VCC 2 15 [] OUT Q/PO [ 3

91000S-60

Abstract: siemens POWER SUPPLY KS 630 S 91000S-70 91000S-80 511000
Contextual Info: S IE M E N S 1 M X 9-Bit Dynamic RAM Module HYM 91000S/-60/-70/-80 Advanced Information • 1 048 576 words by 9-bit organization • Fast access and cycle 60 ns access time 110 ns cycle time -60 70 ns access time 130 ns cycle time (-70 80 ns access time

DS1020-015

Contextual Info: DS1020 DALLAS SEMICONDUCTOR DSI 020 Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay C [2 Q/PO r 3 P1 [ 4 P2 [ 5 P3 [ 6 P4 C7 IN • Models with 0.15 ns, 0.25 ns, 0.5 ns, 1 ns, and 2 ns steps E • Programmable using 3-wire serial port or 8-bit parallel

Contextual Info: POR009 Effective: 5/11/2015 PREFERRED DISTRIBUTOR PRICE LIST PORTABLE CORD Yellow 90 Yellow 90 Yellow 105 Super Vu-Tron Supreme Gauge SOOW SJOOW SOOW SJOOW SOOW SEOOW SJEOOW 18/2 455.11 412.66 NS NS NS 455.11 412.66 18/3 590.57 484.71 618.07 506.94 NS 590.57

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C - JULY 1996 - REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C - JULY 1996 - REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

TMS320C50DU

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Acc 2089

Abstract: TMP320C50KGD TMP320LC50KGD
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Contextual Info: SIEMENS 1 M X 9-Bit Dynamic RAM Module HYM 91000S/-60/-70/-80 Advanced Information • 1 048 576 words by 9-bit organization • Fast access and cycle time 60 ns access time 110 ns cycle time -60 version 70 ns access time 130 ns cycle time (-70 version)

Acc 2089

Abstract: TMP320C50KGD TMP320LC50KGD 446526 Texas instruments military products
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

91000S-70

Abstract: HYM91000S60
Contextual Info: SIEMENS 1 M X 9-Bit Dynamic RAM Module HYM 91000S/-60/-70/-80 Advanced Information • 1 048 576 words by 9-bit organization • Fast access and cycle time 60 ns access time 110 ns cycle time -60 version 70 ns access time 130 ns cycle time (-70 version)

SPRS030

Abstract: 224K-word XDS510PP dsp processor Architecture of TMS320C5X
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

7404

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

Acc 2089

Abstract: TMP320C50KGD TMP320LC50KGD SPRS030
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C − JULY 1996 − REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

DIP18

Abstract: TDA4672 luminance delay
Contextual Info: Philips Semiconductors Product specification Picture Signal Improvement PSI circuit with enhanced peaking function JDA4672 FEATURES • Luminance signal delay from 20 ns to 1100 ns (minimum step 45 ns) • Selectable luminance signal peaking with symmetrical

XT150

Abstract: xt90
Contextual Info: in tj 28F001BX-T/28F001BX-B 1M 128K X 8 CMOS FLASH MEMORY High Integration Blocked Architecture — One 8 KB Boot Block w/Lock Out — Two 4 KB Parameter Blocks — One 112 KB Main Block High-Performance Read — 70/75 ns, 90 ns, 120 ns, 150 ns Maximum Access Time

SMD marking s07

Abstract: smd marking YB smd marking T22 smd code Yj 33 1t211 39S16400 JEM AC3 ml 721 T1-1 P-TSOPII-44 SP 1191
Contextual Info: SIEM EN S 16 MBit Synchronous DRAM • HYB 39S16400/800/160CT-8/-10 High Performance: /c K M A X ?CK3 -8 -10 Units 125 100 MHz 8 10 ns ! AC3 6 7 ?CK2 10 12 ns ?AC2 6 8 ns ns • Multiple Burst Read with Single Write Operation • Autom atic and Controlled Precharge

video luminance delay peaking overshoot

Abstract: TDA4670 IEC 337-2
Contextual Info: Preliminary specification Philips Semiconductors Video Products Picture signal improvement PSI circuit TDA4670 Supersedes data o f August 1990 FEATURES • Luminance signal delay from 20 ns up to 1100 ns (minimum step 45 ns) • Luminance signal peaking with

Contextual Info: VITELIC C0RP w 45E ì> E =5305310 OOOOblS b H V I T V53C104H UL TRA-HIGH PERFORMANCE, LOW POWER 256K X 4 B I T FAST PAGE MODE CMOS DYNAMIC RAM VITELIC ADVANCE INFORMA TION 45/45L 50/50L 55/55L 60/60L Max. RAS Access Time, tRAC 45 ns 50 ns 55 ns 60 ns Max. Column Address Access Time, (tCAA)