NRD NEC Search Results

Contextual Info: 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 7 — 20 November 2012 Product data sheet 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data nD inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

74LV74

Contextual Info: 74LV74-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 1 — 23 September 2013 Product data sheet 1. General description The 74LV74-Q100 is a dual positive edge triggered, D-type flip-flop. It has individual data nD inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and

Contextual Info: 74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 1 — 7 August 2012 Product data sheet 1. General description The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data nD , clock (nCP), set (nSD) and reset (nRD) inputs, and complementary

Contextual Info: 74LVC74A-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 2 — 5 April 2013 Product data sheet 1. General description The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data nD inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ

Contextual Info: 74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 2 — 6 September 2013 Product data sheet 1. General description The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data nD , clock (nCP), set (nSD) and reset (nRD) inputs, and complementary

74HC74

Abstract: 74hc74 pin diagram 74HCT74 74HC74 application HCT74 74HC74N 74HC74DB 74HC74 application note 74HCT74N CI 74hc74
Contextual Info: 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 4 — 27 August 2012 Product data sheet 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data nD , clock (nCP), set (nSD) and reset (nRD) inputs, and complementary

74HC74

Abstract: 74HC74-Q100 74HC74 application note 74HC74 application 74HCT74 CI 74hc74 Current 74HCT74 TTL 74hc74 74hc74 pin diagram 74HC74BQ
Contextual Info: 74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 1 — 7 August 2012 Product data sheet 1. General description The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data nD , clock (nCP), set (nSD) and reset (nRD) inputs, and complementary

74LV74

Contextual Info: 74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 3 — 9 September 2013 Product data sheet 1. General description The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data nD inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ

AN1403

Abstract: NMOS MODEL PARAMETERS SPICE PMOS MODEL PARAMETERS SPICE mj04 74ACxxx 74ACTXXX
Contextual Info: AN1403 Application Note  I/O FACT Model Kit Prepared by Willard Tu FACT Applications Engineering This application note provides the SPICE information necessary to allow the customer to perform system level interconnect modelling for the Motorola FACT logic

AMBA APB bus protocol

Abstract: 1785a1 atmel 0606
Contextual Info: Features • AMBA Compliant Interface • • • • • • • • • • • • • – Interfaces Directly to the ARM Advanced System Bus ASB External Memory Mapping, 512-Mbyte Address Space Up to 8 Chip Select Lines 8- or 16-bit Data Bus Byte Write or Byte Select Lines

atmel 0605

Abstract: AMBA APB bus protocol memory um61m256k-15
Contextual Info: Features • AMBA Compliant Interface • • • • • • • • • • • • • • – Interfaces Directly to the ARM Advanced System Bus ASB External Memory Mapping, 512-Mbyte Address Space Up to 8 Chip Select Lines 8- or 16-bit Data Bus

Contextual Info: Features • AMBA Compliant Interface • • • • • • • • • • • • • – Interfaces Directly to the ARM Advanced System Bus ASB External Memory Mapping, 64-Mbyte Address Space Up to 8 Chip Select Lines 8- or 16-bit Data Bus Byte Write or Byte Select Lines

COM20020

Abstract: COM20019 COM20020D COM20022 HD6417750F167 SH7750 latch ic
Contextual Info: AN 14.2 Design Guidelines for Connecting the ARCNET Product Family, COM20019/20/22, with Renesas Technology’s SH Series Microcontrollers 1 Introduction SMSC’s COM20019, COM20020 and COM20022 ARCNET controllers are designed to be easily connected to all types of microcontrollers. However, special attention to bus timing is recommended

Sandisk NAND Flash memory controller wear levelling

Abstract: Sandisk NAND Flash memory controller wear level Sandisk NAND Flash memory controller ecc Sandisk NAND Flash memory controller wear leveling K9F2G08U0M 6301A ARM at91sam7se AT91SAM7SE nand flash ecc bits K9F2G08U0
Contextual Info: NAND Flash Support on AT91SAM7SE Microcontrollers 1. Scope The purpose of this document is to introduce NAND Flash memory technology and describe hardware and software requirements to interface NAND Flash with the Atmel AT91SAM7SE family of ARM® Thumb®-based microcontrollers.

BIOS Flash ROM Chip

Abstract: 8000h-FFFFh mmc application 8051 0x00h-0xFFh
Contextual Info: APPLICATION NOTE 7.2 GPIO Expansion for the FDC37N95xFR By Nizar Azzam This document is targeted for board designers who require more GPIOs than the provided GPIOs in a given FDC37N95xFR part. The goal is to identify different designs to expand the GPIOs.

ARM microcontroller

Abstract: AT91M40400-25AC AT91M40400 EBI-16 AT91M40400-33AC
Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb Processor • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In Circuit Emulation 4K Bytes Internal RAM

introduction of monostable multivibrator

Abstract: 74HC-HCT123 74HC123D application note hct123 74HCT123N 74HC123N 74HC123D 74HC/HCT/HCU/HCMOS Logic Package Information 74HCT123D IC06 74HC/HCT/HCU/HCMOS Logic Package Information
Contextual Info: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT123

AT91M40400

Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb Processor • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In Circuit Emulation 4K Bytes Internal RAM

1795A

Abstract: AT91EB40A AT91R40008 TQFP100
Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb® Processor Core • • • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Little-endian – Embedded ICE In-circuit Emulation

AT91M40400

Abstract: 25ac M4040025
Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb Processor - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In Circuit Emulation • 4K Bytes Internal RAM • Fully Programmable External Bus Interface EBI

Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb® Processor Core • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In-Circuit Emulation

atmel 042

Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb® Processor Core • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In-Circuit Emulation

ICE2 asic

Contextual Info: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor Core • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In-Circuit Emulation

74HCT123 application note

Abstract: 74hc123 application note
Contextual Info: 74HC123-Q100; 74HCT123-Q100 Dual retriggerable monostable multivibrator with reset Rev. 1 — 1 August 2012 Product data sheet 1. General description The 74HC123-Q100; 74HCT123-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL LSTTL . They are specified in compliance with