NB6N11S/D, AUGUST, 2009 REV. 5 Search Results

NB6N11S/D, AUGUST, 2009 REV. 5 Result Highlights (5)

Part	Manufacturer	Description	Download
67292-009	Amphenol Communications Solutions	BergStik® 2.54mm, Board To Board, Vertical 2 Row Guide Pin Header 18 Positions 2.54mm Pitch 3.81um (150u\\.) Tin-Lead Mating plating.	PDF
10121002-009LF	Amphenol Communications Solutions	HPCE R/A Receptacle 16P12S	PDF
61082-142009LF	Amphenol Communications Solutions	BergStak® 0.80mm Pitch, Receptacle, Vertical, Double Row, 140 Positions.	PDF
59112-T40-20-090LF	Amphenol Communications Solutions	Minitek® 2.00mm, Board To Board, Unshrouded Vertical Stacking Header, Through Hole, Double Row, 40 Positions.	PDF
10119109-372009LF	Amphenol Communications Solutions	BergStik®, Board to Board connector, Unshrouded vertical header, Through Hole, Double Row, 72 Positions, 2.54 mm (0.100in) Pitch.	PDF

NB6N11S/D, AUGUST, 2009 REV. 5 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
NB6N11S/D, August, 2009 Rev. 5 Abstract: 485G EP11 NB6N11S Contextual Info: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical	Original	NB6N11S NB6N11S NB6N11S/D NB6N11S/D, August, 2009 Rev. 5 485G EP11	PDF
NB6N11S Abstract: NB6L11SMNG 485G E5052A E8663B NB6L11S OC48 Contextual Info: NB6L11S 2.5 V 1:2 AnyLevel] Input to LVDS Fanout Buffer / Translator The NB6L11S is a differential 1:2 clock or data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical	Original	NB6L11S NB6L11S NB6L11S/D NB6N11S NB6L11SMNG 485G E5052A E8663B OC48	PDF

Catalog Datasheet

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Document Tags

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NB6N11S/D, August, 2009 Rev. 5

Abstract: 485G EP11 NB6N11S
Contextual Info: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical

Original

NB6N11S NB6N11S NB6N11S/D NB6N11S/D, August, 2009 Rev. 5 485G EP11

PDF

NB6N11S

Abstract: NB6L11SMNG 485G E5052A E8663B NB6L11S OC48
Contextual Info: NB6L11S 2.5 V 1:2 AnyLevel] Input to LVDS Fanout Buffer / Translator The NB6L11S is a differential 1:2 clock or data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical

Original

NB6L11S NB6L11S NB6L11S/D NB6N11S NB6L11SMNG 485G E5052A E8663B OC48

PDF