NB6N11S/D, AUGUST, 2009 REV. 5 Search Results

NB6N11S/D, August, 2009 Rev. 5

Abstract: 485G EP11 NB6N11S
Contextual Info: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical

NB6N11S

Abstract: NB6L11SMNG 485G E5052A E8663B NB6L11S OC48
Contextual Info: NB6L11S 2.5 V 1:2 AnyLevel] Input to LVDS Fanout Buffer / Translator The NB6L11S is a differential 1:2 clock or data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical

Contextual Info: NB6L11S 2.5 V 1:2 AnyLevel] Input to LVDS Fanout Buffer / Translator The NB6L11S is a differential 1:2 clock or data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical